參數(shù)資料
型號(hào): MCF5208CVM166
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Microprocessor Data Sheet
中文描述: 微處理器數(shù)據(jù)表
文件頁(yè)數(shù): 35/46頁(yè)
文件大?。?/td> 936K
代理商: MCF5208CVM166
Preliminary Electrical Characteristics
MCF5208 ColdFire
Microprocessor Data Sheet, Rev. 0.5
Preliminary
Freescale Semiconductor
35
NOTE
Refer to the
MCF5208 Reference Manual
for more information.
5.10 I
2
C Input/Output Timing Specifications
Table 14
and
Table 15
list specifications for the I
2
C input and output timing parameters.
Table 14. I
2
C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2
t
cyc
I2
Clock low period
8
t
cyc
I3
I2C_SCL/I2C_SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V)
1
ms
I4
Data hold time
0
ns
I5
I2C_SCL/I2C_SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V)
1
ms
I6
Clock high time
4
t
cyc
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2
t
cyc
I9
Stop condition setup time
2
t
cyc
Table 15. I
2
C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
1
NOTES:
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table A-16. The I
2
C
interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in Table A-16 are minimum values.
2
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively
drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal
capacitance and pull-up resistor values.
3
Specified at a nominal 50-pF load.
Start condition hold time
6
t
cyc
I2
1.
Clock low period
10
t
cyc
I3
2
I2C_SCL/I2C_SDA rise time (V
IL
= 0.5 V to V
IH
= 2.4 V)
μs
I4
1.
Data hold time
7
t
cyc
I5
3
I2C_SCL/I2C_SDA fall time (V
IH
= 2.4 V to V
IL
= 0.5 V)
3
ns
I6
1.
Clock high time
10
t
cyc
I7
1.
Data setup time
2
t
cyc
I8
1.
Start condition setup time (for repeated start condition only)
20
t
cyc
I9
1.
Stop condition setup time
10
t
cyc
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