參數(shù)資料
型號： MC8641DHX1333JE
廠商： Freescale Semiconductor
文件頁數(shù)： 45/130頁
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
21
DDR and DDR2 SDRAM
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8641. Note that DDR SDRAM is Dn_GVDD(typ) = 2.5 V and DDR2 SDRAM is
Dn_GVDD(typ) = 1.8 V.
6.1
DDR SDRAM DC Electrical Characteristics
Table 13 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
MPC8641 when Dn_GVDD(typ) = 1.8 V.
Table 14 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V.
Table 13. DDR2 SDRAM DC Electrical Characteristics for D
n_GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
D
n_GVDD
1.71
1.89
V
1
I/O reference voltage
D
n_MVREF 0.49 × Dn_GVDD
0.51
× Dn_GVDD
V2
I/O termination voltage
VTT
D
n_MVREF –0.0
4
D
n_MVREF + 0.04
V
3
Input high voltage
VIH
D
n_MVREF+0.1
25
D
n_GVDD +0.3
V
—
Input low voltage
VIL
–0.3
D
n_MVREF – 0.125
V
—
Output leakage current
IOZ
–50
50
μA4
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
—
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
—
Notes:
1. D
n_GVDD is expected to be within 50 mV of the DRAM Dn_GVDD at all times.
2. D
n_MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the
receiver. Peak-to-peak noise on D
n_MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to D
n_MVREF. This rail should track variations in the DC level of Dn_MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ V
OUT ≤ Dn_GVDD.
Table 14. DDR2 SDRAM Capacitance for D
n_GVDD(typ)=1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. D
n_GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2, VOUT
(peak-to-peak) = 0.2 V.
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