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參數(shù)資料
| 型號(hào)： | MC74VHC393M |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual 4-Bit Binary Ripple Counter |
| 中文描述： | AHC/VHC SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14 |
| 封裝： | EIAJ, SOIC-14 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | MC74VHC393M |
MC74VHC393
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
3
MOTOROLA
b l
di i
U i
tPLH,
±
0.5V
8.6
tPHL
CL = 15pF
7.3
65
1.0
35
15.5
ns
Maximum Propagation Delay,
85
115
75
0.3V
13.2
12.7
6.8
19.3
10.5
1.0
1.0
1.0
22.0
11.5
12.0
tPHL
9.8
0.3V
CL = 50pF
VCC = 3.3
0.3V
9.2
13.0
15.5
13.2
Typical @ 25
°
C, VCC = 5.0V
11.7
1.0
1.0
1.0
18.0
15.0
23.0
26.5
1.0
ns
21.0
Maximum Propagation Delay,
tOSLH,
19.7
23.2
VCC = 5.0
±
0.5V
10.4
15.8
8.5
1.0
12.5
18.0
1.0
14.5
4
6.9
10.1
1.0
pF
11.5
(Note NO TAG)
VCC = 3.3
±
0.3V
1.5
1.5
pF
10
10
CPD
Power Dissipation Capacitance (Note NO TAG)
23
pF
1. Parameter guaranteed by design. tOSLH = |tPLHm – tPLHn|, tOSHL = |tPHLm – tPHLn|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR
= CPD VCC fin + ICC/2 (per 4–bit counter). CPD is used to determine
the no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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