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參數(shù)資料
| 型號(hào)： | MC74HCT541AN |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver With LSTTL-Compatible Inputs |
| 中文描述： | HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大?。?/td> | 128K |
| 代理商： | MC74HCT541AN |
MC74HCT541A
http://onsemi.com
3
AC CHARACTERISTICS
(VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
23
28
32
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
30
34
38
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
30
34
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
12
15
18
ns
Cin
Cout
Maximum Input Capacitance
10
10
10
pF
Maximum Three–State Output Capacitance (Output in High Impedance
State)
15
15
15
pF
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
55
CPD
Power Dissipation Capacitance (Per Buffer)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
pF
Figure 1.
CL*
*Includes all probe and jig capacitance
TEST
POINT
OE1 or OE2
1.3V
3.0V
GND
OUTPUT Y
tPZL
OUTPUT Y
tPZH
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
10%
90%
tPLZ
tPHZ
1.3V
1.3V
Figure 2.
SWITCHING WAVEFORMS
DEVICE
UNDER
TEST
OUTPUT
TEST CIRCUITS
Figure 3.
Figure 4.
CL*
*Includes all probe and jig capacitance
TEST
POINT
DEVICE
UNDER
TEST
OUTPUT
1k
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ and tPZH.
3.0V
GND
INPUT A
OUTPUT Y
tPLH
tPHL
90%
1.3V
10%
tr
tTLH
tf
tTHL
90%
1.3V
10%
1.3V
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