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參數(shù)資料
| 型號(hào)： | MC74HCT74ADR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual D Flip−Flop with Set and Reset with LSTTL Compatible Inputs |
| 中文描述： | HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | LEAD FREE, SOIC-14 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 143K |
| 代理商： | MC74HCT74ADR2G |
Semiconductor Components Industries, LLC, 2006
October, 2006
Rev. 10
1
Publication Order Number:
MC74HCT74A/D
MC74HCT74A
Dual D FlipFlop with Set
and Reset with LSTTL
Compatible Inputs
High
Performance Silicon
Gate CMOS
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
This device consists of two D flip
flops with individual Set, Reset,
and Clock inputs. Information at a D
input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip
flop. The Set
and Reset inputs are asynchronous.
Features
Output Drive Capability: 10 LSTTL Loads
TTL NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 A
In Compliance With the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 136 FETs or 34 Equivalent Gates
Pb
Free Packages are Available
LOGIC DIAGRAM
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
PIN 14 = V
CC
PIN 7 = GND
Equivalent to a two
input NAND gate.
http://onsemi.com
MARKING
DIAGRAMS
A
L, WL
Y, YY
W, WW = Work Week
G
= Pb
Free Package
= Assembly Location
= Wafer Lot
= Year
SOIC
14
D SUFFIX
CASE 751A
14
1
HCT74AG
AWLYWW
1
14
14
1
PDIP
14
N SUFFIX
CASE 646
MC74HCT74AN
AWLYYWWG
1
14
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
PIN ASSIGNMENT
SET 1
CLOCK 1
DATA 1
RESET 1
11
12
13
14
8
9
10
5
4
3
2
1
7
6
SET 2
CLOCK 2
DATA 2
RESET 2
V
CC
Q2
Q2
GND
Q1
Q1
FUNCTION TABLE
Inputs
Outputs
Q
H
L
H*
H
L
No Change
No Change
No Change
Set Reset Clock Data
L
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
Q
L
H
H*
L
H
X
X
X
X
X
X
H
L
X
X
X
L
H
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredict-
able if Set and Reset go high simultaneously.
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