參數(shù)資料
型號: MC74HC251N
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: 8-Input Data Selector/Multiplexer with 3-State Outputs
中文描述: HC/UH SERIES, 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 1/7頁
文件大小: 213K
代理商: MC74HC251N
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
"! ! !
"!$ #!
!!"!"!
High–Performance Silicon–Gate CMOS
The MC54/74HC251 is identical in pinout to the LS251. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as determined by
the Address Inputs. The Output Enable pin must be a low level for the
selected data to appear at the outputs. If Output Enable is high, both the Y
and the Y outputs are in the high–impedance state. This 3–state feature
allows the HC251 to be used in bus–oriented systems.
The HC251 is similar in function to the HC151 which does not have
3–state outputs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
LOGIC DIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
OUTPUT ENABLE
Y
Y
DATA
OUTPUTS
DATA
INPUTS
ADDRESS
INPUTS
5
6
4
3
2
1
15
14
13
12
11
10
9
7
PIN 16 = VCC
PIN 8 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Outputs
Output
Enable
A2
A1
A0
Y
Y
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
Z
Z
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Z = high impedance
D0, D1,
, D7 = the level of the respective
D input.
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
D7
D6
D5
D4
VCC
A2
A1
A0
D0
D1
D2
D3
GND
OUTPUT
ENABLE
Y
Y
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
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