參數(shù)資料
型號(hào): MC74HC257D
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Quad 2-Input Data Selector/Multiplexer with 3-State Outputs
中文描述: HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16
封裝: 0.150 INCH, PLASTIC, SOIC-16
文件頁(yè)數(shù): 1/6頁(yè)
文件大小: 175K
代理商: MC74HC257D
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
" "! !
!"!$ #!
!!"!"!
High–Performance Silicon–Gate CMOS
The MC74HC257 is identical in pinout to the LS257. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device selects a (4–bit) nibble from either the A or B inputs as
determined by the Select input. The nibble is presented at the outputs in
noninverted form when the Output Enable pin is at a low level. A high level on
the Output Enable pin switches the outputs into the high–impedance state.
The HC257 is similar in function to the HC157 which do not have 3–state
outputs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 108 FETs or 27 Equivalent Gates
LOGIC DIAGRAM
2
5
11
14
3
6
10
13
4
7
9
12
1
15
A0
A1
A2
A3
B0
B1
B2
B3
Y0
Y1
Y2
Y3
SELECT
OUTPUT
ENABLE
NONINVERTING
NIBBLE
OUTPUT
NIBBLE
A INPUT
NIBBLE
B INPUT
PIN 16 = VCC
PIN 8 = GND
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
Y3
B3
A3
OUTPUT
ENABLE
VCC
Y2
B2
A2
Y0
B0
A0
SELECT
GND
Y1
B1
A1
FUNCTION TABLE
Inputs
Outputs
Output
Enable
Select
Y0 – Y3
H
L
L
X
L
H
Z
A0 – A3
B0 – B3
X = don’t care
Z = high impedance
A0–A3, B0–B3 = the levels of the
respective Nibble Inputs.
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
1
16
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
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