參數(shù)資料
型號： MC7457VG867NC
廠商： Freescale Semiconductor
文件頁數(shù)： 66/71頁
文件大?。?/td> 0K
描述： IC MPU RISC 867MHZ 483FCCBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC74xx
處理器類型： 32-位 MPC74xx PowerPC
速度： 867MHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 483-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 483-FCCBGA（29x29）
包裝： 托盤
Document Revision History
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
69
4
Table 9: Corrected pin lists for input and output AC timing to correctly show HIT as an output-only
signal
Added specifications for 1267 MHz devices; removed specs for 1300 MHz devices.
Section 5.2.3: Changed recommendations regarding use of L3 clock jitter in AC timing analysis. The
L3 jitter is now fully comprehended in the AC timing specs and does not need to be included in the
timing analysis.
3
Corrected numerous errors in lists of pins associated with tKHOV, tKHOX, tIVKH, and tIXKH in Table 9.
Added support for 1.5 V L3 interface voltage; issues fixed in Rev. 1.1.
Corrected typos in Table 12.
Added data to Table 2.
Clarified address bus pull-up resistor recommendations in Section 1.9.6.
Modified Table 9, Figure 5, and Figure 6 to more accurately show when the mode select inputs
(BMODE[0:1], L3VSEL, BVSEL) are sampled and AC timing requirements
Table 10: Added skew and jitter values.
Table 14: Added AC timing values.
Table 24: Updated to reflect past and current part numbers not fully covered by this document.
Table 6: Removed CVIH and CVIL; VIH and VIL for SYSCLK input is the same as for other input
signals, and is now noted accordingly in this table.
Table 7: Removed Doze mode power entry (but left footnote 4 for clarity); documentation change
only.
Nontechnical formatting
2
Added substrate capacitor information in Sections 1.8.3 and 1.8.6.
Increased minimum processor and VCO frequencies in Table 8 from 500 and 1000 MHz to 600 and
1200 MHz (respectively).
Corrected maximum processor frequency for 1300 MHz devices in Table 8 (changed from 1333 to
1300 MHz).
Added value for to tL3CSKW1 Table 10.
Added L3OHCR information in Section 1.5.2.4.1.
Added values for tCO and tECI to Table 11.
Added Note 8 to Table 13 and Note 6 to Table 14.
Changed resistor value in PLL filter in Figure 25 from 10
Ω to 400 Ω.
Added 867 MHz speed grade.
Corrected Product Code in Tables 22 and 23.
Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 1.9.6.
1.1
Nontechnical reformatting.
Table 26. Document Revision History (continued)
Revision
Number
Date
Substantive Change(s)
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