參數(shù)資料
型號(hào): MC7457VG867NC
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 55/71頁(yè)
文件大?。?/td> 0K
描述: IC MPU RISC 867MHZ 483FCCBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC74xx
處理器類(lèi)型: 32-位 MPC74xx PowerPC
速度: 867MHz
電壓: 1.1V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 483-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 483-FCCBGA(29x29)
包裝: 托盤(pán)
System Design Information
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
59
Figure 26. JTAG Interface Connection
HRESET
From Target
Board Sources
HRESET
13
SRESET
11
VDD_SENSE
6
5 1
15
2 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
OVDD
CHKSTP_IN
8
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
9
1
3
4
TRST
7
16
2
10
(if any)
COP
He
ade
r
14 2
Key
QACK
OVDD
10 k
Ω
OVDD
TRST
10 k
Ω
OVDD
10 k
Ω
10 k
Ω
QACK
CHKSTP_OUT
3
13
9
5
1
6
10
2
15
11
7
16
12
8
4
KEY
No Pin
COP Connector
Physical Pin Out
10 k
Ω 4
OVDD
1
2 k
Ω 3
0
Ω 5
12 6
NC
Notes:
1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7457. Connect
pin 5 of the COP header to OVDD with a 10-kΩ pull-up resistor.
2. Key location; pin 14 is not physically present on the COP header.
3. Component not populated. Populate only if debug tool does not drive QACK.
4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK.
5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP
header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect
HRESET from the target source to TRST of the part through a 0-
Ω isolation resistor.
6. Though defined as a No-Connect, it is a common and recommended practice to use pin 12 as an
additional GND pin for improved signal integrity.
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