參數(shù)資料
型號(hào): MC7455ARX867LF
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁(yè)數(shù): 30/64頁(yè)
文件大?。?/td> 1127K
代理商: MC7455ARX867LF
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
30
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 12
shows the L3 bus timing diagrams for the MPC7455 interfaced to PB2 or late write SRAMs.
Figure 12. L3 Bus Timing Diagrams for Late Write or PB2 SRAMs
5.2.5 IEEE 1149.1 AC Timing Specifications
Table 14
provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in
Figure 14
through
Figure 17
.
Table 14. JTAG AC Timing Specifications (Independent of SYSCLK)
1
At recommended operating conditions. See
Table 4
.
Parameter
Symbol
Min
Max
Unit
Notes
TCK frequency of operation
f
TCLK
0
33.3
MHz
TCK cycle time
t
TCLK
30
ns
TCK clock pulse width measured at 1.4 V
t
JHJL
15
ns
TCK rise and fall times
t
JR
and t
JF
0
2
ns
TRST assert time
t
TRST
25
ns
2
Input setup times:
Boundary-scan data
TMS, TDI
t
DVJH
t
IVJH
4
0
ns
3
Input hold times:
Boundary-scan data
TMS, TDI
t
DXJH
t
IXJH
20
25
ns
3
L3_ECHO_CLK[0,2]
L3 Data and Data
VM
VM = Midpoint Voltage (GV
DD
/2)
t
L3DVEH
t
L3DXEH
Parity Inputs
L3_CLK[0,1]
ADDR, L3_CNTL
VM
t
L3CHOV
t
L3CHOX
VM
L3DATA WRITE
t
L3CHDZ
Outputs
Inputs
L3_ECHO_CLK[1,3]
t
L3CHDV
t
L3CHDX
t
L3CHOZ
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