參數(shù)資料
型號： MC68LC302PU20VCT
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數(shù)： 85/128頁
文件大?。?/td> 641K
代理商： MC68LC302PU20VCT
MOTOROLA
MC68EN302 USER’S MANUAL
vii
TABLE OF CONTENTS
Paragraph
Title
Page
Number
Section 1
Introduction
1.1
Feature List ............................................................................................. 1-1
1.2
Block Diagram......................................................................................... 1-2
1.3
Memory Map ........................................................................................... 1-2
1.3.1
Module Controller Base Address Register (MOBAR) Address ($EE) ..... 1-3
1.4
Register Overview................................................................................... 1-3
Section 2
MC68EN302 Module Bus Controller
2.1
Introduction ............................................................................................. 2-1
2.2
Top Level Memory Map .......................................................................... 2-2
2.3
MBC Registers ........................................................................................ 2-2
2.4
Module Bus Control (MBCTL) ................................................................. 2-2
2.5
Interrupt Extension Register (IER) .......................................................... 2-3
2.6
Chip Select Extension Registers (CSER3–CSER0) ............................... 2-4
2.7
Parity Control and Status Register (PCSR) ............................................ 2-6
2.8
Bus Interface ........................................................................................... 2-7
2.8.1
Bus Arbitration......................................................................................... 2-7
2.9
Dynamic Bus Sizing ................................................................................ 2-7
2.9.1
Bus Cycle Timing .................................................................................... 2-9
2.9.2
Bus Error Handling................................................................................ 2-10
2.9.3
Retry Handling ...................................................................................... 2-11
2.10
Parity Logic ........................................................................................... 2-11
2.10.1
Parity Generation .................................................................................. 2-11
2.10.2
Parity Checking ..................................................................................... 2-11
2.10.3
Parity Error Reporting ........................................................................... 2-11
2.10.4
Parity Pin Enable................................................................................... 2-12
2.11
Interrupt Support ................................................................................... 2-12
Section 3
MC68EN302 DRAM Control Module
3.1
Introduction ............................................................................................ 3-1
3.2
Memory Map .......................................................................................... 3-1
3.3
DRAM Configuration Register (DCR)..................................................... 3-1
3.4
DRAM Refresh Register (DRFRSH) ...................................................... 3-2
3.5
DRAM Base Address Register (DBA1-DBA0) ....................................... 3-3
3.6
DRAM Control Module Operation .......................................................... 3-3
3.6.1
Reset Operation ..................................................................................... 3-3
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