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參數(shù)資料
| 型號(hào)： | MC68LC302PU20VCT |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁(yè)數(shù)： | 104/128頁(yè) |
| 文件大?。?/td> | 641K |
| 代理商： | MC68LC302PU20VCT |
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Signal Descriptions
5-10
MC68EN302 REFERENCE MANUAL
MOTOROLA
The MC68EN302 DISCPU state is sampled during hardware reset just as in the MC68302.
The M68000 core is disabled by asserting the DISCPU pin high during total system reset.
5.5.15 PARITY1/BUSW
Parity is controlled by the PCSR Register in the module bus controller. This bidirectional pin
provides even or odd parity for byte 1 (bit 7–bit 0) when not in the reset state.
The state of BUSW is sampled during total system reset. When the BUSW is low during
hardware reset, it does not put the 68000 into 68008 mode with an 8 bit bus. Instead, having
the BUSW low during hardware reset will force the four EN8 bits in the CSER registers to
one, enabling support for dynamic bus sizing in the chip selects. Note that because the
68000 core is in normal 16 bit mode, if the 68000 accesses memory outside of the four chip
select areas, it always performs a normal 16 bit access.
5.5.16 PARITYE/THREESTATE
During normal operation, this bidirectional pin is the active low PARITYE (parity error)
output, and is asserted whenever one of the PED (Parity Error DRAM) bits in the PCSR is
asserted.
If this pin is low during total system reset, all bidirectional pins and output pins will be put
into three-state mode. This is intended for chip test purposes.
5.6 DRAM CONTROLLER I/O
5.6.1 Control Signal Pins
The EN302 contains 8 DRAM specific signal pins: CAS1–CAS0, RAS1–RAS0, AMUX, and
DRAMRW.
5.6.2 Column Address Strobes (CAS1–CAS0)
These active low pins allow seamless interface to Column Address Strobe (CAS) inputs on
industry standard DRAM, providing CAS for both bank 0 and bank 1 of the DRAM controller.
Two strobes support byte operations on the external 16-bit bus. CAS0 corresponds to data
pins D15-D8. CAS1 corresponds to data pins D7–D0.
5.6.3 Row Address Strobes (RAS1–RAS0)
These active low pins allow seamless interface to Row Address Strobe (RAS) inputs on
industry standard DRAM, providing RAS for both bytes of a given DRAM bank. A particular
bank corresponds to specific Base Address and Control information programmed in the
MC68EN302 DRAM control registers (see 3.2 Memory Map for a description). RAS0
corresponds to bank 0 and RAS1 corresponds to Bank 1.
5.6.4 DRAM Read/Write (DRAMRW)
This active low pin is asserted to signify that a DRAM write cycle is occurring. It is separate
from the processor bus R/W so that precharge takes place without regard to the state of R/
W.
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