
MOTOROLA
MC68LC302 REFERENCE MANUAL
v
TABLE OF CONTENTS
Paragraph
Title
Page
Number
Section 1
Introduction
1.1
Block Diagram......................................................................................... 1-1
1.2
Features .................................................................................................. 1-2
1.3
LC302 Applications ................................................................................. 1-3
1.4
LC302 Differences .................................................................................. 1-3
Section 2
Configuration, Clocking, Low Power Modes, and Internal Memory Map
2.1
MC68LC302 and MC68302 Signal Differences ...................................... 2-1
2.2
IMP Configuration Control....................................................................... 2-2
2.2.1
Base Address Register ........................................................................... 2-4
2.3
System Configuration Registers.............................................................. 2-5
2.4
Clock Generation and Low Power Control .............................................. 2-5
2.4.1
PLL and Oscillator Changes to IMP ........................................................ 2-5
2.4.1.1
Clock Control Register ............................................................................ 2-6
2.4.2
MC68LC302 System Clock Generation .................................................. 2-6
2.4.2.1
Default System Clock Generation ........................................................... 2-7
2.4.3
IMP System Clock Generation ................................................................ 2-8
2.4.3.1
System Clock Configuration.................................................................... 2-8
2.4.3.2
On-Chip Oscillator................................................................................... 2-8
2.4.3.3
Phase-Locked Loop (PLL) ...................................................................... 2-9
2.4.3.4
Frequency Multiplication ......................................................................... 2-9
2.4.3.4.1
Low Power PLL Clock Divider............................................................... 2-10
2.4.3.4.2
IMP PLL and Clock Control Register (IPLCR) ...................................... 2-10
2.4.3.5
IMP Internal Clock Signals .................................................................... 2-12
2.4.3.5.1
IMP System Clock................................................................................. 2-12
2.4.3.5.2
BRG Clock ............................................................................................ 2-12
2.4.3.5.3
PIT Clock............................................................................................... 2-12
2.4.3.6
IMP PLL Pins ........................................................................................ 2-12
2.4.3.6.1
VCCSYN ............................................................................................... 2-12
2.4.3.6.2
GNDSYN............................................................................................... 2-12
2.4.3.6.3
XFC ....................................................................................................... 2-12
2.4.3.6.4
MODCLK............................................................................................... 2-12
2.4.4
IMP Power Management....................................................................... 2-13
2.4.4.1
IMP Low Power Modes ......................................................................... 2-13
2.4.4.1.1
STOP Mode .......................................................................................... 2-13
2.4.4.1.2
DOZE Mode .......................................................................................... 2-13
2.4.4.1.3
STAND_BY Mode ................................................................................. 2-13