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參數(shù)資料
| 型號： | MC68L11FC0PU4 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, MICROCONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 59/74頁 |
| 文件大小： | 513K |
| 代理商： | MC68L11FC0PU4 |
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MOTOROLA
MC68HC11F1/FC0
62
MC68HC11FTS/D
OCxF — Output Compare x Flag
Set each time the counter matches output compare x value.
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL.
ICxF — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line.
Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables the
corresponding interrupt source. TMSK2 can be written only once in the first 64 cycles out of reset in
normal modes, or at any time in special modes.
TOI — Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled
1 = Interrupt requested when TOF is set
RTII — Real-Time Interrupt Enable
0 = Real-time interrupt disabled
1 = Interrupt requested when RTIF is set
Bits [5:4] — See 13.2 Pulse Accumulator Registers, page 64.
Bits [3:2] — Not implemented. Reads always return zero and writes have no effect.
PR[1:0] — Timer Prescaler Select
Determines the main timer prescale factor as shown in Table 31. See Table 26 for specific frequencies.
Bits in this register indicate when certain timer system events have occurred. Coupled with the four
high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled or
interrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.
Bits in TFLG2 are cleared by writing a one to the corresponding bit positions.
TOF — Timer Overflow Flag
Set when TCNT rolls over from $FFFF to $0000.
TMSK2 — Timer Interrupt Mask 2
$x024
Bit 7
6
5
4
3
2
1
Bit 0
TOI
RTII
PAOVI
PAII
0
PR1
PR0
RESET:
0
Table 31 Main Timer Prescale Control
PR[1:0]
Prescaler
0 0
1
0 1
4
1 0
8
1 1
16
TFLG2 — Timer Interrupt Flag 2
$x025
Bit 7
6
5
4
3
2
1
Bit 0
TOF
RTIF
PAOVF
PAIF
0000
RESET:
0
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