參數(shù)資料
型號: MC68L11FC0PU4
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: Technical Summary 8-Bit Microcontroller
中文描述: 8-BIT, MICROCONTROLLER, PQFP80
封裝: TQFP-80
文件頁數(shù): 42/74頁
文件大?。?/td> 513K
代理商: MC68L11FC0PU4
MC68HC11F1/FC0
MOTOROLA
MC68HC11FTS/D
47
RWU — Receiver Wake Up Control
0 = Normal SCI receiver
1 = Wake up enabled and receiver interrupt inhibited
SBK — Send Break
0 = Break generator off
1 = Break codes generated as long as SBK = 1
TDRE — Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then
writing to SCDR.
0 = SCDR is busy
1 = SCDR is empty
TC — Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
the TC flag by reading SCSR with TC set and then writing to SCDR.
0 = Transmitter is busy
1 = Transmitter is idle
RDRF — Receive Data Register Full Flag
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR with RDRF set and then reading SCDR.
0 = SCDR empty
1 = SCDR full
IDLE — Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR
with IDLE set and then reading SCDR.
0 = RxD line is active
1 = RxD line is idle
OR — Overrun Error Flag
OR is set if a new character is received before a previously received character is read from SCDR. Clear
OR by reading SCSR with OR set and then reading SCDR.
0 = No overrun detected
1 = Overrun detected
NF — Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading
SCSR with NF set and then reading SCDR.
0 = Unanimous decision
1 = Noise detected
FE — Framing Error
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR
with FE set and then reading SCDR.
0 = Stop bit detected
1 = Zero detected
SCSR — SCI Status Register
$x02E
Bit 7
6
5
4
3
2
1
Bit 0
TDRE
TC
RDRF
IDLE
OR
NF
FE
0
RESET:
1
0
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