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參數(shù)資料
| 型號： | MC68HSC05P1ADW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 97/124頁 |
| 文件大?。?/td> | 623K |
| 代理商： | MC68HSC05P1ADW |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
16-Bit Timer
General Release Specification
MC68HC05P1A — Rev. 3.0
74
16-Bit Timer
MOTOROLA
8.7 Timer Status Register
Reading the timer status register (TSR) satisfies the first condition
required to clear status flags and interrupts. The only remaining step is
to read (or write) the register associated with the active status flag
(and/or interrupt). This method does not present any problems for input
capture or output compare functions.
However, a problem can occur when using a timer interrupt function and
reading the free-running counter at random times to measure an elapsed
time. If the proper precautions are not designed into the application
software, a timer interrupt flag (TOF) could unintentionally be cleared if:
1. The TSR is read when bit 5 (TOF) is set.
2. The LSB of the free-running counter is read, but not for the
purpose of servicing the flag or interrupt.
The alternate counter registers (ACRH and ACRL) contain the same
values as the timer registers (TMRH and TMRL). Registers ACRH and
ACRL can be read at any time without affecting the timer overflow flag
(TOF) or interrupt.
ICF — Input Capture Flag
Bit 7 is set when the edge specified by IEDG in register TCR has been
sensed by the input capture edge detector fed by pin TCAP. This flag
and the input capture interrupt can be cleared by reading register TSR
followed by reading the LSB of the input capture register pair (ICRL).
$0013
Bit 7
654321
Bit 0
Read:
ICF
OCF
TOF
00000
Write:
Reset:
U
00000
U = Unaffected
Figure 8-12. Timer Status Register (TSR)
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