參數(shù)資料
型號： MC68HC711D3CFN2
廠商： Freescale Semiconductor
文件頁數(shù)： 117/124頁
文件大?。?/td> 0K
描述： IC MCU 2MHZ 4K OTP 44-PLCC
標準包裝： 26
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 2MHz
連通性： SCI，SPI
外圍設備： POR，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 4KB（4K x 8）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-LCC（J 形引線）
包裝： 管件
TIMING SYSTEM
9-6
TECHNICAL DATA
9.2.2 Timer Input Capture Registers
When an edge has been detected and synchronized, the 16-bit free-running counter
value is transferred into the input capture register pair as a single 16-bit parallel trans-
fer. Timer counter value captures and timer counter incrementing occur on opposite
half-cycles of the phase two clock so that the count value is stable whenever a capture
occurs. The TICx registers are not affected by reset. Input capture values can be read
from a pair of 8-bit read-only registers. A read of the high-order byte of an input capture
register pair inhibits a new capture transfer for one bus cycle. If a double-byte read in-
struction, such as LDD, is used to read the captured value, coherency is assured.
When a new input capture occurs immediately after a high-order byte read, transfer is
delayed for an additional cycle but the value is not lost.
9.2.3 Timer Input Capture 4/Output Compare 5 Register
Use TI4/O5 as either an input capture register or an output compare register, depend-
ing on the function chosen for the I4/O5 pin. To enable it as an input capture pin, set
the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level one. To
use it as an output compare register, set the I4/O5 bit to a logic level zero. Refer to 9.6
9.3 Output Compare
Use the output compare (OC) function to program an action to occur at a specific time
— when the 16-bit counter reaches a specified value. For each of the five output com-
pare functions, there is a separate 16-bit compare register and a dedicated 16-bit com-
parator. The value in the compare register is compared to the value of the free-running
counter on every bus cycle. When the compare register matches the counter value, an
output compare status flag is set. The flag can be used to initiate the automatic actions
for that output compare function.
To produce a pulse of a specific duration, write to the output compare register a value
representing the time the leading edge of the pulse is to occur. The output compare
circuit is configured to set the appropriate output either high or low, depending on the
TIC1–TIC3 — Timer Input Capture
$0010–$0015
$0010
Bit 15
14
13
12
11
10
9
Bit 8
TIC1 (High)
$0011
Bit 7
654321
Bit 0
TIC1 (Low)
$0012
Bit 15
14
13
12
11
10
9
Bit 8
TIC2 (High)
$0013
Bit 7
654321
Bit 0
TIC2 (Low)
$0014
Bit 15
14
13
12
11
10
9
Bit 8
TIC3 (High)
$0015
Bit 7
654321
Bit 0
TIC3 (Low)
RESET:
Input capture registers not affected by reset.
TI4/O5 — Timer Input Capture 4/Output Compare 5
$001E, $001F
$001E
Bit 15
14
13
12
11
10
9
Bit 8
TI4/O5 (High)
$001F
Bit 7
6
5
4
3
2
1
Bit 0
TI4/O5 (Low)
RESET:
All I4/O5 register pairs reset to ones ($FFFF).
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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