參數(shù)資料
型號(hào): MC68HC705P6ACDW
廠商: Freescale Semiconductor
文件頁數(shù): 52/98頁
文件大?。?/td> 0K
描述: IC MCU 2.1MHZ 4.5K OTP 28-SOIC
標(biāo)準(zhǔn)包裝: 26
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 4.5KB(4.5K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
Analog Subsystem
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
56
Freescale Semiconductor
9.7 A/D Subsystem Operation during Halt/Wait Modes
The A/D subsystem continues normal operation during wait and halt modes. To decrease power
consumption during wait or halt mode, the ADON and ADRC bits in the A/D status and control register
should be cleared if the A/D subsystem is not being used.
9.8 A/D Subsystem Operation during Stop Mode
When stop mode is enabled, execution of the STOP instruction will terminate all A/D subsystem functions.
Any pending conversion is aborted. When the oscillator resumes operation upon leaving stop mode, a
finite amount of time passes before the A/D subsystem stabilizes sufficiently to provide conversions at its
rated accuracy. The delays built into the MC68HC705P6A when coming out of stop mode are sufficient
for this purpose. No explicit delays need to be added to the application software.
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