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參數(shù)資料
| 型號： | MC68HC705L1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 36/102頁 |
| 文件大?。?/td> | 632K |
| 代理商： | MC68HC705L1B |
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MC68HC05L1
MOTOROLA
5-3
PROGRAMMABLE TIMER
5
5.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2
s if the internal bus clock is 2MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
5.1.1
Counter Register and Alternate Counter Register
The double-byte, free-running counter can be read from either of two locations, $18 & $19 (counter
register) or $1A & $1B (alternate counter register). Reading only the least signicant byte (LSB)
of the free-running counter ($19 or $1B) receives the count value at the time of the read. If the
most signicant byte (MSB) ($18 or $1A) is read rst, the LSB ($19 or $1B) is transferred to a
buffer. This buffer value remains xed after the rst MSB read, even if the MSB is read several
times. This buffer is accessed when the LSB ($19 or $1B) is read, and thus, completes a read
sequence of the complete counter value.
Reading the timer counter register low byte after reading the timer status register clears the timer
overow ag (TOF), but reading the alternate counter register does not affect TOF. Therefore, the
alternate counter register can be read any time without risk of missing timer overow interrupts
due to a cleared TOF.
The free-running counter is preset to $FFFC during reset and is always a read-only register.
During a power-on reset, the counter is also preset to $FFFC and begins running after the
oscillator start-up delay. The value in the free-running counter repeats every 262144 internal bus
clock cycles.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer counter high
$0018
$FF
Timer counter low
$0019
$FC
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Alternate counter high
$001A
$FF
Alternate counter low
$001B
$FC
TPG
37
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