參數(shù)資料
型號: MC68HC11K1
廠商: Motorola, Inc.
元件分類: 8位微控制器
英文描述: 8-Bit Microcontroller(8位微控制器)
中文描述: 8位微控制器(8位微控制器)
文件頁數(shù): 7/20頁
文件大?。?/td> 286K
代理商: MC68HC11K1
AN1242/D
MOTOROLA
7
THE SOLUTION
Before proceeding with a design solution based on a WSI PSD4XX or PSD5XX device, it is instructive to
review the problem as it now stands.
The existing MC68HC711K4-based system makes extensive use of the integrated MCU peripheral
resources. In particular, the SCI connects to an ASCII terminal that simplifies interactive user control.
Size reductions specified for the next generation of this product are best achieved by replacing the
ASCII terminal with a keyboard and LCD panel that are integrated with the control unit.
The digital I/O requirements for the keyboard and LCD interfaces could exhaust the MC68HC711K4
I/O resources.
Application storage demands increase for two reasons. The keyboard and LCD panel require addition-
al interface code, and the firmware is to be ported from assembly language to C.
To support the proposed expansion of storage capacity from 24 Kbytes to 64 Kbytes, the MCU must
use expanded operating mode rather than single-chip operating mode.
Expanded mode operation requires at least 25 pins for the non-multiplexed address/data bus and the
read/write line. These pins are currently used for digital I/O. Other digital I/O pins must be used to
support chip selects and memory expansion beyond 64 Kbytes.
It appears that the proposed system would require a 32 Kbyte EPROM for control routines, another 32 Kbyte
EPROM for LCD data tables, several latches to rebuild lost I/O ports, and some programmable logic to map
all of these devices into the MC68HC711K4 address space. This design clearly jeopardizes cost savings
achieved by the existing implementation and future high-level language software development.
Some of the savings can be restored by switching MCUs. The 24 Kbyte EPROM on the MC68HC711K4 is
not needed for the new design, so either the ROM-less MC68HC11K1 or the ROM-and-EEPROM-less
MC68HC11K0 could be used. These devices retain the specialized peripherals available on the
MC68HC(7)11K4, and are ideal for expanded mode applications where the I/O pins used by the bus inter-
face are not required or are otherwise rebuilt.
Both cost reduction and increased flexibility can be achieved by using a WSI PSD4XX or PSD5XX program-
mable system device in place of the memory and logic components that would otherwise be needed to re-
alize this design.
As shown in
logic resources. If subsequent specifications dictate increased memory, logic, or even peripheral function-
ality, other members of the PSD4XX and PSD5XX families could be used, while maintaining close compat-
ibility with the PSD412A1.
Table 4
and
Table 5
, a PSD412A1 can easily provide the required additional memory, I/O, and
Table 1
proposed MC68HC11K(0/1) + PSD412A1 system
compares the memory, I/O, and logic resources of both the initial MC68HC711K4 system and the
.
In essence, the combination of a non-multiplexed bus M68HC11 MCU and a PSD4XX or PSD5XX device
restores much of the functionality of a single-chip system. While not providing the ultimate size and power
consumption features of such a design, the increased flexibility of this pairing and the freedom it provides
to system designers is a competitive advantage.
Table 1 M68HC11 Single-Chip versus M68HC11 + PSD4XX Resource Comparison
MC68HC711K4
24 Kbytes
768 bytes
640 bytes
54 lines
None
None
None
MC68HC11K(0/1) + PSD412A1
16 Kbytes + 16 Kbytes + 32 Kbytes = 64 Kbytes
768 + 2048 = 2816 bytes
640 bytes/0 bytes
61 lines
61
113
8
EPROM
SRAM
EEPROM
Available Bi-directional I/O
PLD input terms
PLD product terms
Registered Macro Cells
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