參數(shù)資料
型號(hào)： MC68HC11K0VFU3
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁(yè)數(shù)： 32/80頁(yè)
文件大?。?/td> 420K
代理商： MC68HC11K0VFU3
MOTOROLA
32
M68HC11 K Series
MC68HC11KTS/D
4.3.3 General-Purpose Chip Selects (CSGP1, CSGP2)
The general-purpose chip selects are the most flexible and programmable and have the most control
bits. Polarity of active state, E valid or address valid, size, and starting address are all programmable.
Clock stretching can be set from zero to three cycles. Each chip select can be programmed to become
active whenever the CPU address enters a memory expansion window regardless of the actual bank
selected. This is known as following a window.
Each general purpose chip select can be configured to drive the program chip select. CSGP1 can be
configured to drive CSGP2 or the program chip select. Using one chip select to drive another allows the
same device to cover the address space defined by both chip selects. The two chip selects are con-
nected to an internal OR gate. The output of the OR gate is then driven onto the pin corresponding to
the driven chip select. For example, this is useful when the same external device is used with both bank
windows but the windows are opened independently. In cases where one chip select drives another,
determine the priority from the following table.
4.3.4 Chip Select Priorities
To minimize chip select conflicts (with one another or with internal memory and registers), the priority
is determined by the GCSPR bit in the CSCTL register. Refer to the following table.
4.3.5 Chip Select Control Registers
There are six chip select control registers. Chip select functions are enabled by control bits in CSCTL
register. Chip selects are configured by bits in CSCSTR, IOEN, IOPL, IOCSA, and IOSZ registers.
IOEN —I/O Chip Select Enable
0 = CSIO disabled
1 = CSIO enabled
IOPL —I/O Chip Select Polarity Select
0 = CSIO active low
1 = CSIO active high
Condition
Priority
GPCS1
GPCS1
GPCS2
GPCS1
GPCS1 drives GPCS2
GPCS1 drives PCS
GPCS2 drives PCS
GPCS1 and GPCS2 drive PCS
GCSPR = 0
On-Chip Registers
On-Chip RAM
Bootloader ROM
On-Chip EEPROM
On-Chip ROM/EPROM
I/O Chip Select
Program Chip Select
GP Chip Select 1
GP Chip Select 2
GCSPR = 1
On-Chip Registers
On-Chip RAM
Bootloader ROM
On-Chip EEPROM
On-Chip ROM/EPROM
I/O Chip Select
GP Chip Select 1
GP Chip Select 2
Program Chip Select
CSCTL
—
Chip Select Control
$005B
Bit 7
IOEN
0
6
5
4
3
2
1
Bit 0
PCSZB
0
IOPL
0
IOCSA
0
IOSZ
0
GCSPR
0
PCSEN
1
PCSZA
0
RESET:
相關(guān)PDF資料
PDF描述
MC68HC11K0VFU4 8-BIT MICROCONTROLLER
MC68L11K0FN1 8-BIT MICROCONTROLLER
MC68L11K0FN3 8-BIT MICROCONTROLLER
MC68L11K0FU1 8-BIT MICROCONTROLLER
MC68L11K0FU3 8-BIT MICROCONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC11K0VFU4 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontroller
MC68HC11K1 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS Microcontroller Unit
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MC68HC11K1CFN3 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT
MC68HC11K1CFN4 功能描述:IC MCU 640 EEPROM 4MHZ 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND
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