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參數(shù)資料
| 型號： | MC68HC11C0FN3 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 54/76頁 |
| 文件大?。?/td> | 394K |
| 代理商： | MC68HC11C0FN3 |
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MOTOROLA
MC68HC11C0
58
MC68HC11C0TS/D
Notes:
1. If a pin is configured for general-purpose I/O, the DDRD bit controls the direction of data.
2. If a pin is configured as SS, the MSTR and DDRD bits are the output enable.
3. SPE is the SPI enable bit, MSTR is the master/slave select bit. Refer to the SPCR register.
4. IRQ or SS inputs are internally pulled high if not used. This does not affect the pin.
Notes:
1. If a pin is configured for general-purpose I/O, the DDRD bit controls the direction of data.
2. If a pin is configured as MOSI, the MSTR and DDRD bit control the direction of data.
3. SPE is the SPI enable bit, MSTR is the master/slave select bit. Refer to the SPCR register.
Notes:
1. If a pin is configured for general-purpose I/O, the DDRD bit controls the direction of data.
2. If a pin is configured as MISO, the MSTR and DDRD bit control the direction of data.
3. SPE is the SPI enable bit, MSTR is the master/slave select bit. Refer to the SPCR register.
4. XIRQ or MISO inputs are internally pulled high if not used. This does not affect the pin.
Table 12 PD5 Configuration
SPI Enable
DIOCTL
Bit 5
DIOCTL
Bit 4
PD5
Pull-Up
Control
Output
Enable
SPE = 0
0
X
I/O
DDD5
1
0
IRQ
On
Off
1
I/O
DDD5
SPE = 1
0
X
I/O
DDD5
1
0
IRQ
On
Off
11
SS
Off
MSTR + DDD5
Table 13 PD[4:3] Configuration
SPI Enable
PD4
PD3
Pull-Up
Control
Output
Enable
SPE = 0
I/O
DDD[4:3]
SPE = 1
MOSI
SCK
Off
MSTR + DDD[4:3]
Table 14 PD2 Configuration
SPI Enable
DIOCTL
Bit 3
DIOCTL
Bit 2
PD2
Pull-Up
Control
Output
Enable
SPE = 0
0
X
I/O
DDD[3:2]
1
0
XIRQ
On
Off
1
I/O
DDD[3:2]
SPE = 1
0
X
I/O
DDD[3:2]
1
0
XIRQ
On
Off
1
MISO
Off
MSTR + DDD[3:2]
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