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| 型號： | MC68HC11A0CFU4 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | ROM-based high-performance microcontrollers |
| 中文描述： | 基于ROM的高性能微控制器 |
| 文件頁數(shù)： | 7/124頁 |
| 文件大小： | 840K |
| 代理商： | MC68HC11A0CFU4 |
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MC68HC11D3
TA
Figure
Title
Page
LIST OF ILLUSTRATIONS
1-1
MC68HC11D3 Block Diagram ........................................................................ 1-2
2-1
2-2
2-3
2-4
2-5
2-6
Pin Assignments for 44-Pin PLCC ................................................................. 2-1
Pin Assignments for 40-Pin DIP ..................................................................... 2-2
External Reset Circuit ..................................................................................... 2-3
Common Crystal Connections ........................................................................ 2-3
External Oscillator Connections ..................................................................... 2-4
One Crystal Driving Two MCUs ..................................................................... 2-4
3-2
Programming Model ....................................................................................... 3-1
Stacking Operations ....................................................................................... 3-3
4-1
4-2
4-3
Address/Data Demultiplexing ......................................................................... 4-2
MC68HC11D3 Memory Map .......................................................................... 4-3
RAM Standby MODB/V
STBY
Connections ...................................................... 4-6
5-1
5-2
5-3
Processing Flow out of Reset (1 of 2) .......................................................... 5-12
Interrupt Priority Resolution (1 of 2) ............................................................. 5-14
Interrupt Source Resolution within SCI ........................................................ 5-16
7-1
7-2
7-3
7-4
SCI Transmitter Block Diagram ...................................................................... 7-2
SCI Receiver Block Diagram .......................................................................... 7-3
SCI Baud Rate Diagram ............................................................................... 7-10
Interrupt Source Resolution within SCI ........................................................ 7-12
8-1
8-2
SPI Block Diagram ......................................................................................... 8-2
SPI Transfer Format ....................................................................................... 8-3
9-1
9-2
9-3
Timer Clock Divider Chains ............................................................................ 9-2
Capture/Compare Block Diagram .................................................................. 9-4
Pulse Accumulator ....................................................................................... 9-16
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
Test Methods ..................................................................................................A-3
Timer Inputs ...................................................................................................A-4
POR and External Reset Timing Diagram ......................................................A-5
STOP Recovery Timing Diagram ...................................................................A-6
WAIT Recovery Timing Diagram ....................................................................A-7
Port Write Timing Diagram .............................................................................A-8
Port Read Timing Diagram .............................................................................A-8
Multiplexed Expansion Bus Timing Diagram ................................................A-10
SPI Master Timing (CPHA = 0) ....................................................................A-12
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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