參數(shù)資料
型號: MC68HC11A0CFU1
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: ROM-based high-performance microcontrollers
中文描述: 基于ROM的高性能微控制器
文件頁數(shù): 100/124頁
文件大?。?/td> 840K
代理商: MC68HC11A0CFU1
TIMING SYSTEM
9-14
TECHNICAL DATA
Clear flags by writing a one to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to one at the end of every RTI period. To clear
RTIF, write a byte to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
Refer to
9.6 Pulse Accumulator
.
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Refer to
9.6 Pulse Accumulator
.
Bits [3:0] — Not implemented
Always read zero
9.4.2 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the real-time interrupt system. Bit
DDRA3 determines whether Port A bit three is an input or an output when used for
general-purpose I/O. The remaining bits control the pulse accumulator.
DDRA7 — Data Direction Control for Port A Bit 7
Refer to
9.6 Pulse Accumulator
.
PAEN — Pulse Accumulator System Enable
Refer to
9.6 Pulse Accumulator
.
PAMOD — Pulse Accumulator Mode
Refer to
9.6 Pulse Accumulator
.
PEDGE — Pulse Accumulator Edge Control
Refer to
9.6 Pulse Accumulator
.
DDRA3 — Data Direction Register for Port A Bit 3
Refer to
SECTION 6 PARALLEL I/O
.
I4/O5 — Input Capture 4/Output Compare 5
Refer to
9.2 Input Capture
.
TFLG2
— Timer Interrupt Flag 2
$0025
Bit 7
TOF
0
6
5
4
3
0
0
2
0
0
1
0
0
Bit 0
0
0
RTIF
0
PAOVF
0
PAIF
0
RESET:
PACTL
— Pulse Accumulator Control
$0026
Bit 7
DDRA7
0
6
5
4
3
2
1
Bit 0
RTR0
0
PAEN
0
PAMOD
0
PEDGE
0
DDRA3
0
I4/O5
0
RTR1
0
RESET:
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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