參數(shù)資料
型號(hào)： MC68HC11A0CFN1
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： ROM-based high-performance microcontrollers
中文描述： 基于ROM的高性能微控制器
文件頁數(shù)： 53/124頁
文件大?。?/td> 840K
代理商： MC68HC11A0CFN1
RESETS AND INTERRUPTS
TECHNICAL DATA
5-9
5.4.1 Interrupt Recognition and Register Stacking
An interrupt can be recognized at any time after it is enabled by its local mask, if any,
and by the global mask bit in the CCR. Once an interrupt source is recognized, the
CPU responds at the completion of the instruction being executed. Interrupt latency
varies according to the number of cycles required to complete the current instruction.
When the CPU begins to service an interrupt, the contents of the CPU registers are
pushed onto the stack in the order shown in
Table 5-5
. After the CCR value is stacked,
the I bit and the X bit, if XIRQ is pending, are set to inhibit further interrupts. The inter-
rupt vector for the highest priority pending source is fetched, and execution continues
at the address specified by the vector. At the end of the interrupt service routine, the
return from interrupt instruction is executed and the saved registers are pulled from the
stack in reverse order so that normal program execution can resume. Refer to
SEC-
TION 3 CENTRAL PROCESSING UNIT
for further information.
Table 5-4 Interrupt and Reset Vector Assignments
Vector Address
Interrupt Source
CCR Mask
Local
Mask
—
—
TCIE
TIE
ILIE
RIE
RIE
SPIE
PAII
PAOVI
TOI
I4/O5I
OC4I
OC3I
OC2I
OC1I
IC3I
IC2I
IC1I
RTII
None
None
None
None
NOCOP
CME
None
FFC0, C1 — FFD4, D5
FFD6, D7
Reserved
SCI Serial System
SCI Transmit Complete
SCI Transmit Data Register Empty
SCI Idle Line Detect
SCI Receiver Overrun
SCI Receive Data Register Full
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real Time Interrupt
IRQ (External Pin)
XIRQ Pin
Software Interrupt
Illegal Opcode Trap
COP Failure
Clock Monitor Fail
RESET
—
I Bit
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE2, E3
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
X Bit
None
None
None
None
None
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC11A0CFN2 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller
MC68HC11A0CFN3 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述:
MC68HC11A0CFN3R2 制造商:Rochester Electronics LLC 功能描述:
MC68HC11A0CFN4 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers
MC68HC11A0CFNE3 功能描述:8位微控制器 -MCU 8B MCU 768RAM A/D 3MH RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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