參數(shù)資料
型號： MC68HC08QY2VDTE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.65 MM PITCH, LEAD FREE, TSSOP-16
文件頁數(shù)： 47/176頁
文件大?。?/td> 1124K
代理商： MC68HC08QY2VDTE
Development Support
MC68HC08QY/QT Family Data Sheet, Rev. 2
140
Freescale Semiconductor
Figure 15-10. Monitor Mode Circuit (External Clock, with High Voltage)
The monitor code has been updated from previous versions of the monitor code to allow enabling the
internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is returned to
normal logic levels after a reset into monitor mode is entered, is intended to support serial communication
at 9600 baud in monitor mode by using the internal oscillator, and the internal oscillator user trim value
OSCTRIM (ROM location $FFC0) to generate the desired internal frequency (3.2 MHz). The IRQ pin must
remain at normal logic levels during the monitor session in order to maintain communication.
Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
may be entered after a power-on reset (POR).
The rising edge of the internal RST signal with VTST applied to IRQ latches the monitor mode. Once
monitor mode is latched, the values on PTA1 and PTA4 pins can be changed.
Once out of reset, the MCU waits for the host to send eight security bytes (see 15.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
9.8304 MHz CLOCK
+
10 kΩ
*
VDD
10 kΩ
*
RST (PTA3)
IRQ (PTA2)
PTA0
OSC1 (PTA5)
8
7
DB9
2
3
5
16
15
2
6
10
9
VDD
MAX232
V+
V–
1 μF
+
1
2
3
4
5
6
74HC125
10 kΩ
PTA1
PTA4
VSS
0.1 μF
VDD
1 kΩ
9.1 V
C1+
C1–
5
4
1 μF
C2+
C2–
+
3
1
1 μF
+
1 μF
VDD
+
1 μF
VTST
* Value not critical
VDD
10 kΩ
*
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