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參數(shù)資料
| 型號： | MC68HC08QY2MDT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.65 MM PITCH, TSSOP-16 |
| 文件頁數(shù)： | 162/178頁 |
| 文件大?。?/td> | 2311K |
| 代理商： | MC68HC08QY2MDT |
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Low-Voltage Inhibit (LVI)
MC68HC08QY/QT Family Data Sheet, Rev. 1
84
Freescale Semiconductor
The LVI module contains a bandgap reference circuit and comparator. When the LVITRIP bit is cleared,
the default state at power-on reset, VTRIPF is configured for the lower VDD operating range. The actual
trip points are specified in 16.5 5-V DC Electrical Characteristics, 16.8 3-V DC Electrical Characteristics,
Because the default LVI trip point after power-on reset is configured for low voltage operation, a system
requiring high voltage LVI operation must set the LVITRIP bit during system initialization. VDD must be
above the LVI trip rising voltage, VTRIPR, for the high voltage operating range or the MCU will immediately
go into LVI reset.
After an LVI reset occurs, the MCU remains in reset until VDD rises above VTRIPR. See Chapter 13 System
Integration Module (SIM) for the reset recovery sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and
can be used for polling LVI operation when the LVI reset is disabled.
The LVI is enabled out of reset. The following bits located in the configuration register can alter the default
conditions.
Setting the LVI power disable bit, LVIPWRD, disables the LVI.
Setting the LVI reset disable bit, LVIRSTD, prevents the LVI module from generating a reset.
Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode.
Setting the LVI trip point bit, LVITRIP, configures the trip point voltage (VTRIPF) for the higher VDD
operating range.
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling
the LVIOUT bit. In the configuration register, LVIPWRD must be cleared to enable the LVI module, and
LVIRSTD must be set to disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI
module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, LVIPWRD
and LVIRSTD must be cleared to enable the LVI module and to enable LVI resets.
10.3.3 LVI Hysteresis
The LVI has hysteresis to maintain a stable operating condition. After the LVI has triggered (by having
VDD fall below VTRIPF), the MCU will remain in reset until VDD rises above the rising trip point voltage,
VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is
approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the typical hysteresis voltage, VHYS.
10.3.4 LVI Trip Selection
LVITRIP in the configuration register selects the LVI protection range. The default setting out of reset is
for the low voltage range. Because LVITRIP is in a write-once configuration register, the protection range
cannot be changed after initialization.
NOTE
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (VTRIPF) may be lower than this. See the Electrical Characteristics
section for the actual trip point voltages.
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