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參數(shù)資料
| 型號(hào)： | MC68HC08QY2MDT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.65 MM PITCH, TSSOP-16 |
| 文件頁(yè)數(shù)： | 117/178頁(yè) |
| 文件大?。?/td> | 2311K |
| 代理商： | MC68HC08QY2MDT |
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Registers
MC68HC08QY/QT Family Data Sheet, Rev. 1
Freescale Semiconductor
43
3.8.4 ADC10 Clock Register (ADCLK)
This register selects the clock frequency for the ADC10 and the modes of operation.
ADLPC — ADC10 Low-Power Configuration Bit
ADLPC controls the speed and power configuration of the successive approximation converter. This
is used to optimize power consumption when higher sample rates are not required.
1 = Low-power configuration: The power is reduced at the expense of maximum clock speed.
0 = High-speed configuration
ADIV[1:0] — ADC10 Clock Divider Bits
ADIV1 and ADIV0 select the divide ratio used by the ADC10 to generate the internal clock ADCK.
Table 3-3 shows the available clock configurations.
ADICLK — Input Clock Select Bit
If ACLKEN is clear, ADICLK selects either the bus clock or an alternate clock source as the input clock
source to generate the internal clock ADCK. If the alternate clock source is less than the minimum
clock speed, use the internally-generated bus clock as the clock source. As long as the internal clock
ADCK, which is equal to the selected input clock divided by ADIV, is at a frequency (fADCK) between
the minimum and maximum clock speeds (considering ALPC), correct operation can be guaranteed.
1 = The internal bus clock is selected as the input clock source
0 = The alternate clock source IS SELECTED
MODE[1:0] — 10- or 8-Bit or Hardware Triggered Mode Selection
These bits select 10- or 8-bit operation. The successive approximation converter generates a result
that is rounded to 8- or 10-bit value based on the mode selection. This rounding process sets the
transfer function to transition at the midpoint between the ideal code voltages, causing a quantization
error of ± 1/2LSB.
Reset returns 8-bit mode.
00 = 8-bit, right-justified, ADCSC software triggered mode enabled
01 = 10-bit, right-justified, ADCSC software triggered mode enabled
10 = Reserved
11 = 10-bit, right-justified, hardware triggered mode enabled
Bit 7
654321
Bit 0
Read:
ADLPC
ADIV1
ADIV0
ADICLK
MODE1
MODE0
ADLSMP
ACLKEN
Write:
Reset:
00000000
Figure 3-7. ADC10 Clock Register (ADCLK)
Table 3-3. ADC10 Clock Divide Ratio
ADIV1
ADIV0
Divide Ratio (ADIV)
Clock Rate
0
1
Input clock
÷ 1
0
1
2
Input clock
÷ 2
1
0
4
Input clock
÷ 4
1
8
Input clock
÷ 8
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