參數(shù)資料
型號: MC68HC08QY1VDWE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝: 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-013AA, SOIC-16
文件頁數(shù): 31/178頁
文件大小: 2311K
代理商: MC68HC08QY1VDWE
Timer Interface Module (TIM)
MC68HC08QY/QT Family Data Sheet, Rev. 1
126
Freescale Semiconductor
14.7 I/O Signals
The TIM module can share its pins with the general-purpose I/O pins. See Figure 14-1 for the port pins
that are shared.
14.7.1 TIM Channel I/O Pins (TCH1:TCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
TCH0
can be configured as buffered output compare or buffered PWM pin.
14.7.2 TIM Clock Pin (TCLK)
TCLK is an external clock input that can be the clock source for the counter instead of the prescaled
internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS[2:0]. See
14.8.1 TIM Status and Control Register. The minimum TCLK pulse width is specified in the Timer
Interface Module Characteristics table in the Electricals section. The maximum TCLK frequency is the
least of 4 MHz or bus frequency
÷ 2.
14.8 Registers
The following registers control and monitor operation of the TIM:
TIM status and control register (TSC)
TIM control registers (TCNTH:TCNTL)
TIM counter modulo registers (TMODH:TMODL)
TIM channel status and control registers (TSC0 and TSC1)
TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
14.8.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
Enables TIM overflow interrupts
Flags TIM overflows
Stops the counter
Resets the counter
Prescales the counter clock
TOF — TIM Overflow Flag Bit
This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter
modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing a 0 to TOF.
Bit 7
654321
Bit 0
Read:
TOF
TOIE
TSTOP
00
PS2
PS1
PS0
Write:
0
TRST
Reset:
00100000
= Unimplemented
Figure 14-4. TIM Status and Control Register (TSC)
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