參數資料
型號： MC68HC08QY1VDWE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 1.27 MM PITCH, LEAD FREE, PLASTIC, MS-013AA, SOIC-16
文件頁數： 19/178頁
文件大?。?/td> 2311K
代理商： MC68HC08QY1VDWE
Low-Power Modes
MC68HC08QY/QT Family Data Sheet, Rev. 1
Freescale Semiconductor
115
In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the
module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode
sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD,
in the configuration register is 0, then the computer operating properly module (COP) is enabled and
remains active in wait mode.
Figure 13-15 and Figure 13-16 show the timing for wait recovery.
Figure 13-15. Wait Recovery from Interrupt
Figure 13-16. Wait Recovery from Internal Reset
13.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU
and peripherals. If OSCENINSTOP is set, BUSCLKX2 will remain running in STOP and can be used to
run the AWU. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles
down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
$6E0C
$6E0B
$00FF
$00FE
$00FD
$00FC
$A6
$01
$0B
$6E
$A6
ADDRESS BUS
DATA BUS
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt
ADDRESS BUS
DATA BUS
RST(1)
$A6
$6E0B
RSTVCTH
RSTVCTL
$A6
BUSCLKX4
32
CYCLES
32
CYCLES
1. RST is only available if the RSTEN bit in the CONFIG2 register is set.
相關PDF資料
PDF描述
MC68HC08QT4VDW 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
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