參數(shù)資料
型號: MC68HC08QT2CDW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO8
封裝: EIAJ, SOIC-8
文件頁數(shù): 33/178頁
文件大?。?/td> 2311K
代理商: MC68HC08QT2CDW
Timer Interface Module (TIM)
MC68HC08QY/QT Family Data Sheet, Rev. 1
128
Freescale Semiconductor
14.8.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes of the value in the counter.
Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent
reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter
registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by
reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
14.8.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the counter. When the counter reaches
the modulo value, the overflow flag (TOF) becomes set, and the counter resumes counting from $0000
at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until
the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
NOTE
Reset the counter before writing to the TIM counter modulo registers.
Bit 7
654321
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
00000000
= Unimplemented
Figure 14-5. TIM Counter High Register (TCNTH)
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
00000000
= Unimplemented
Figure 14-6. TIM Counter Low Register (TCNTL)
Bit 7
654321
Bit 0
Read:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Write:
Reset:
11111111
Figure 14-7. TIM Counter Modulo High Register (TMODH)
Bit 7
654321
Bit 0
Read:
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Write:
Reset:
11111111
Figure 14-8. TIM Counter Modulo Low Register (TMODL)
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