
Functional Controller Module (FCM)
Functional Controller Registers
MC68HC(9)08LJ60 — Rev. 1.0
Advance Information
MOTOROLA
Functional Controller Module (FCM)
153
NON-DISCLOSURE
AGREEMENT
REQUIRED
MINF — Minutes flag
MINF is a status bit indicating that the minutes counter 1 has rolled
over. Reset clears MINF. A CPU interrupt will be generated if the
MINIE bit is set in the RTCCR.
0 = Flag cleared by a read of the RTC status register with the MINF
flag set, followed by a read of the minutes register. Both read
operations need not be consecutive.
1 = Flag automatically set at 1 minute intervals
SECF — Seconds flag
SECF is a status bit indicating that the seconds counter 1-Hz interval
has elapsed. Reset clears SECF. A CPU interrupt will be generated if
the SECIE bit is set in the RTCCR.
0 = Flag cleared by a read of the RTC status register with the SECF
flag set, followed by a read of the seconds register. Both read
operations need not be consecutive.
1 = Flag automatically set at 1-Hz intervals
AFLG — Alarm flag
AFLG is a status bit indicating that the hours counter matches the
alarm hours register and the minutes counter matches the alarm
minutes register. Reset clears AFLG. A CPU interrupt will be
generated if the ALIEN bit is set in the RTCCR.
0 = Flag cleared by a read of the RTC status register with the AFLG
flag set, followed by a read of the alarm minutes register. Both
read operations need not be consecutive.
1 = Flag automatically set at scheduled alarm time
CHRF — Chronograph flag
CHRF is a status bit indicating that the chronograph 10-Hz interval
has elapsed. A CPU interrupt request will be generated if CHRIE is
set. Reset clears CHRF.
0 = Flag cleared by a read of the RTC status register with the
CHRF flag set, followed by a read of the chronograph data
register. Both read operations need not be consecutive.
1 = Flag automatically set at 10-Hz intervals
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Freescale Semiconductor, Inc.
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