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參數(shù)資料
| 型號： | MC68HC05J1AVP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 68/128頁 |
| 文件大?。?/td> | 1279K |
| 代理商： | MC68HC05J1AVP |
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Technical Data
MC68HC05J1A — Rev. 3.0
44
Interrupts
MOTOROLA
Interrupts
4.3.2.2 PA3–PA0 Pins
The mask option for port A external interrupts enables pins PA3–PA0 to
serve as additional external interrupt sources. An interrupt signal on a
PA3–PA0 pin latches an external interrupt request. After completing the
current instruction, the CPU tests the IRQ latch. If the IRQ latch is set,
the CPU then tests the I bit in the condition code register and the IRQE
bit in the interrupt status and control register. If the I bit is clear and the
IRQE bit is set, the CPU then begins the interrupt sequence. The CPU
clears the IRQ latch while it fetches the interrupt vector, so that another
external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt,
the CPU can recognize the new interrupt request.
External interrupt triggering sensitivity is a mask option. The PA3–PA0
pins can be positive edge-triggered only or positive edge- and high
level-triggered.
With the mask option for an edge- and level-sensitive external interrupt
trigger, a rising edge or a high level on a PA3–PA0 pin latches an
external interrupt request. Edge- and level-sensitive triggering allows the
use of multiple wired-OR external interrupt sources. As long as any
source is holding a PA3–PA0 pin high, an external interrupt request is
latched, and the CPU continues to execute the interrupt service routine.
With the mask option for an edge-sensitive only external interrupt trigger,
a rising edge on a PA3–PA0 pin latches an external interrupt request. A
subsequent external interrupt request can be latched only after the
voltage level of the previous interrupt signal returns to logic 0 and then
rises again to logic 1.
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