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參數(shù)資料
| 型號： | MC68EC000EI8R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 85MHZ 68-PLCC |
| 標準包裝： | 250 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 8MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（25x25） |
| 包裝： | 帶卷 (TR) |
9
M68000 USER’S MANUAL ADDENDUM
MOTOROLA
4.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS
Replace Figure 10-2 on page 10-6 with Figure 7.
Figure 7. Drive Levels and Test Points for AC Specications - applies to all parts
0.8 V
2.0 V
B
DRIVE TO
0.5 V
2.0 V
0.8 V
VALID
OUTPUT n
VALID
OUTPUT
n + 1
2.0 V
0.8 V
2.0 V
0.8 V
2.0 V
0.8 V
VALID
OUTPUT n
VALID
OUTPUT n+1
2.0 V
0.8 V
B
A
VALID
INPUT
2.0 V
0.8 V
2.0 V
0.8 V
D
C
DRIVE TO
0.5 V
DRIVE TO
2.4 V
VALID
INPUT
2.0 V
0.8 V
2.0 V
0.8 V
D
C
DRIVE
TO 0.5 V
DRIVE
TO 2.4 V
2.0 V
0.8 V
2.0 V
0.8 V
F
CLK
OUTPUTS(1) CLK
OUTPUTS(2) CLK
INPUTS(3) CLK
INPUTS(4) CLK
ALL SIGNALS(5)
NOTES:
1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
LEGEND:
A. Maximum output delay specification.
B. Minimum output hold time.
C. Minimum input setup time specification.
D. Minimum input hold time specification.
E. Signal valid to signal valid specification (maximum or minimum).
F. Signal valid to signal invalid specification (maximum or minimum).
DRIVE
TO 2.4 V
E
A
F
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S
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o
n
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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