
10/31/95
SECTION 1: OVERVIEW
UM Rev 1
MOTOROLA
MC68341 USER'S MANUAL
xix
LIST OF ILLUSTRATIONS
Figure
Page
Number
Title
Number
1-1
MC68341 Simplified Block Diagram ............................................................. 1-1
2-1
Functional Signal Groups ............................................................................. 2-2
3-1
Input Sample Window .................................................................................. 3-3
3-2
MC68341 Interface to Various Port Sizes .................................................... 3-9
3-3
Long-Word Operand Read Timing from 8-Bit Port ....................................... 3-13
3-4
Long-Word Operand Write Timing to 8-Bit Port ........................................... 3-14
3-5
Long-Word and Word Read and Write Timing—16-Bit Port......................... 3-15
3-6
Fast Termination Timing............................................................................... 3-17
3-7
Word Read Cycle Flowchart......................................................................... 3-19
3-8
Read Cycle Timing ....................................................................................... 3-20
3-9
68000 Word Read Cycle Flowchart ............................................................. 3-21
3-10
68000 Read Cycle Timing ............................................................................ 3-23
3-11
Word Write Cycle Flowchart ......................................................................... 3-24
3-12
M68300 Write Cycle Timing ......................................................................... 3-25
3-13
68000 Word Write Cycle Flowchart.............................................................. 3-26
3-14
68000 Write Cycle Timing ............................................................................ 3-28
3-15
Read-Modify-Write Cycle Timing ................................................................. 3-29
3-16
CPU Space Address Encoding .................................................................... 3-31
3-17
Breakpoint Operation Flowchart ................................................................... 3-33
3-18
Breakpoint Acknowledge Cycle Timing (Opcode Returned) ........................ 3-34
3-19
Breakpoint Acknowledge Cycle Timing (Exception Signaled) ...................... 3-35
3-20
Interrupt Acknowledge Cycle Flowchart ....................................................... 3-37
3-21
Interrupt Acknowledge Cycle Timing............................................................ 3-38
3-22
Autovector Operation Timing ....................................................................... 3-40
3-23
Bus Error without DSACK≈ ........................................................................... 3-44
3-24
Late Bus Error with DSACK≈ ........................................................................ 3-45
3-25
Retry Sequence ........................................................................................... 3-46
3-26
Late Retry Sequence ................................................................................... 3-47
3-27
HALT Timing ................................................................................................. 3-48
3-28
Bus Arbitration Flowchart for Single Request .............................................. 3-50
3-29
Bus Arbitration Timing Diagram—Idle Bus Case ......................................... 3-51
3-30
Bus Arbitration Timing Diagram—Active Bus Case ..................................... 3-51
3-31
Bus Arbitration State Diagram ...................................................................... 3-54
3-32
Show Cycle Timing Diagram ........................................................................ 3-55
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.