MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-41
D
I4/O5
I4/O5F
Input Capture 4/Output Compare 5
Input Capture 4/Output Compare 5
Flag
I4/O5 Interrupt Enable
Interrupt Arbitration
Input Capture Flags
Input Capture Interrupt Enable
Idle-Line Detected
Idle-Line Interrupt Enable
Interrupt Level for QSPI
Interrupt Level for SCI
Idle-Line Detect Type
Increment Prescaler
Interrupt Vector Number
Interrupt Priority Mask
Interrupt Priority Adjust
Interrupt Priority Level
Interrupt Vector Base Address
Loss of Clock Reset
QSPI Loop Mode
Loop Mode
Mode Select
Module Mapping
Asynchronous/Synchronous Mode
Mode Fault Flag
Master/Slave Mode Select
Negative Flag
New Queue Pointer Value
Noise Error
OC1 Data
OC1 Mask
Output Compare Flags
Output Compare Interrupt Enable
Output Compare Mode Bits
Output Compare Level Bits
Overrun Error
Pulse Accumulator Clock Select
(Gated Mode)
Pulse Accumulator Counter
Pulse Accumulator Enable
Pulse Accumulator Flag
Pulse Accumulator Input Interrupt
Enable
PAI Pin State (Read Only)
Pulse Accumulator Mode
Pulse Accumulator Overflow Flag
Pulse Accumulator Overflow Interrupt
Enable
Port C Data
PACNT
TFLG1
I4/O5I
IARB[3:0]
ICF[3:1]
ICI[3:1]
IDLE
ILIE
ILQSPI
ILSCI
ILT
INCP
INTV[7:0]
IP[2:0]
IPA
IPL
IVBA
LOC
LOOPQ
LOOPS
M
MM
MODE
MODF
MSTR
N
NEWQP
NF
OC1D[5:1]
OC1M[5:1]
OCF[4:1]
OCI[4:1]
OM[5:2]
OL[5:2]
OR
PACLK[1:0]
TMSK1
GPTMCR, QSMCR, SIMCR
TFLG1
TMSK1
SCSR
SCCR1
QILR
QILR
SCCR1
GPTMCR
QIVR
SR
ICR
CSOR[0:10], CSORBT, ICR
ICR
RSR
SPCR3
SCCR1
SCCR1
SIMCR
CSOR[0:10], CSORBT
SPSR
SPCR0
CCR
SPCR2
SCSR
OC1D
OC1M
TFLG1
TMSK1
TCTL1
TCTL1
SCSR
PACNT
PACNT
PAEN
PAIF
PAII
PACNT
PACNT
TFLG2
TMSK2
PAIS
PAMOD
PAOVF
PAOVI
PACNT
PACNT
TFLG2
TMSK2
PC[6:0]
PORTC
Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
Name
Register Location