MC68331
USER’S MANUAL
ELECTRICAL CHARACTERISTICS
MOTOROLA
A-9
A
39
39A
46
46A
47A
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
Asynchronous Input Hold Time
DSACK[1:0] Asserted to BERR, HALT Asserted
11
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time
Mode Select Hold Time
RESET Assertion Time
12
RESET Rise Time
13
t
GH
t
GA
t
RWA
t
RWAS
t
AIST
2
1
—
—
—
—
—
t
cyc
t
cyc
ns
ns
ns
150
90
5
47B
48
53
54
55
56
57
70
71
72
73
74
75
76
77
78
t
AIHT
t
DABA
t
DOCH
t
CHDH
t
RADC
t
HRPW
t
BNHN
t
SCLDD
t
SCLDS
t
SCLDH
t
BKST
t
BKHT
t
MSS
t
MSH
t
RSTA
t
RSTR
15
—
0
—
40
512
0
0
15
10
15
10
20
0
4
—
—
30
—
28
—
—
—
29
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
t
cyc
ns
ns
ns
ns
ns
ns
t
cyc
ns
t
cyc
t
cyc
Table A-6a 20.97 MHz AC Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
Num
F1
1
1A
1B
2, 3
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time
3
4, 5
Clock Rise and Fall Time
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
4B, 5B External Clock Rise and Fall Time
4
6
Clock High to Address, FC, SIZE, RMC Valid
7
Clock High to Address, Data, FC, SIZE, RMC High Impedance
8
Clock High to Address, FC, SIZE, RMC Invalid
9
Clock Low to AS, DS, CS Asserted
9A
AS to DS or CS Asserted (Read)
5
9C
Clock Low to IFETCH, IPIPE Asserted
11
Address, FC, SIZE, RMC Valid
to AS, CS Asserted
12
Clock Low to AS, DS, CS Negated
12A
Clock Low to IFETCH, IPIPE Negated
13
AS, DS, CS Negated to
Address, FC, SIZE Invalid (Address Hold)
Characteristic
Symbol
f
t
cyc
t
Ecyc
t
Xcyc
t
CW
t
ECW
t
XCHL
t
Crf
t
rf
t
XCrf
t
CHAV
t
CHAZx
t
CHAZn
t
CLSA
t
STSA
t
CLIA
t
AVSA
Min
0.13
47.7
381
47.7
18.8
183
23.8
—
—
—
0
0
0
0
–10
2
10
Max
20.97
—
—
—
—
—
—
5
8
5
23
47
—
23
10
22
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Frequency of Operation (32.768 kHz crystal)
2
Clock Period
ECLK Period
External Clock Input Period
3
Clock Pulse Width
t
CLSN
t
CLIN
t
SNAI
2
2
10
23
22
—
ns
ns
ns
Table A-6 16.78 MHz AC Timing, (Continued)
(V
DD
and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
Num
Characteristic
Symbol
Min
Max
Unit