![](http://datasheet.mmic.net.cn/280000/MC68000_datasheet_16093696/MC68000_320.png)
Electrical Characteristics
6-32
MC68302 USER’S MANUAL
MOTOROLA
6.20 AC ELECTRICAL SPECIFICATIONS—GCI TIMING
GCI supports the NORMAL mode and the GCI channel 0 (GCN0) in MUX mode. Normal
mode uses 512 kHz clock rate (256K bit rate). MUX mode uses 256 x n - 3088 kbs (clock
rate is data rate x 2). The ratio CLKO/L1CLK must be greater than 2.5/1 (see Figure 6-21).
NOTES:
1.The ratio CLKO/L1CLK must be greater than 2.5/1.
2. Condition CL = 150 pF. L1TD becomes valid after the L1CLK rising edge or L1SY1, whichever is later.
3.SDS1–SDS2 become valid after the L1CLK rising edge or L1SY1, whichever is later.
4.Schmitt trigger used on input buffer.
5.Where P = 1/CLKO. Thus, for a 16.67-MHz CLKO rate, P = 60 ns.
16.67 MHz
20 MHz
25 MHz
Num.
Characteristic
Min
Max
Min
Max
Min
Max
Unit
L1CLK GCI Clock Frequency (Normal Mode) (see
Note 1)
L1CLK Clock Period Normal Mode (see Note 1)
L1CLK Width Low/High Normal Mode
L1CLK Rise/Fall Time Normal Mode (see Note 4)
L1CLK (GCI Clock) Frequency (MUX Mode) (see
Note 1)
L1CLK Clock Period MUX Mode (see Note 1)
L1CLK Width Low MUX Mode
L1CLK Width High MUX Mode (see Note 5)
L1CLK Rise/Fall Time MUX Mode (see Note 4)
L1SY1 Sync Setup Time to L1CLK Falling Edge
L1SY1 Sync Hold Time from L1CLK Falling Edge
L1TxD Active Delay (from L1CLK Rising Edge) (see
Note 2)
L1TxD Active Delay (from L1SY1 Rising Edge) (see
Note 2)
L1RxD Setup Time to L1CLK Rising Edge
L1RxD Hold Time from L1CLK Rising Edge
—
512
—
512
—
512
kHz
280
281
282
1800
840
—
2100
1450
—
1800
840
—
2100
1450
—
1800
840
—
2100
1450
—
ns
ns
ns
—
6.668
—
6.668
—
6.668
MHz
280
281
281A
282
283
284
150
55
P+10
—
30
50
—
—
—
—
—
—
150
55
P+10
—
25
42
—
—
—
—
—
—
150
55
P+10
—
20
34
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
285
0
100
0
85
0
70
ns
286
0
100
0
85
0
70
ns
287
288
20
50
64
192
—
—
—
—
17
42
64
192
—
—
—
—
14
34
64
192
—
—
—
—
ns
ns
289
Time Between Successive L1SY1in Normal
SCIT Mode
L1CLK
L1CLK
290
SDS1–SDS2 Active Delay from L1CLK Rising Edge
(see Note 3)
SDS1–SDS2 Active Delay from L1SY1 Rising Edge
(see Note 3)
SDS1–SDS2 Inactive Delay from L1CLK Falling
Edge
GCIDCL (GCI Data Clock) Active Delay
10
90
10
75
7
60
ns
291
10
90
10
75
7
60
ns
292
10
90
10
75
7
60
ns
293
0
50
0
42
0
34
ns