參數(shù)資料
型號: MC56F8346
廠商: Motorola, Inc.
英文描述: 56F8346 16-bit Hybrid Controller
中文描述: 56F8346 16位混合控制器
文件頁數(shù): 39/160頁
文件大?。?/td> 1415K
代理商: MC56F8346
Data Map
56F8346 Technical Data
Preliminary
39
4.4 Data Map
Reserved
SCI0
71
0-2
P:$8E
SCI 0 Receiver Error
SCI0
72
0-2
P:$90
SCI 0 Receiver Full
ADCB
73
0-2
P:$92
ADC B Conversion Compete
ADCA
74
0-2
P:$94
ADC A Conversion Complete
ADCB
75
0-2
P:$96
ADC B Zero Crossing of Limit Error
ADCA
76
0-2
P:$98
ADC A Zero Crossing of Limit Error
PWMB
77
0-2
P:$9A
Reload PWM B
PWMA
78
0-2
P:$9C
Reload PWM A
PWMB
79
0-2
P:$9E
PWM B Fault
PWMA
80
0-2
P:$A0
PWM A Fault
core
1.
from the vector table, providing only 19 bits of address.
81
- 1
P:$A2
SW Interrupt LP
Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
2. If the VBA is set to 0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the chip
reset addresses; therefore, these locations are not interrupt vectors.
2.
Table 4-6 Data Memory Map
1
1.
All addresses are 16-bit Word addresses, not byte addresses.
Begin/End
Address
EX = 0
2
2.
In the Operation Mode Register (OMR).
EX = 1
X:$FF FFFF
X:$FF FF00
EOnCE
256 locations allocated
EOnCE
256 locations allocated
X:$FF FEFF
X:$01 0000
External Memory
External Memory
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 2000
External Memory
External Memory
X:$00 1FFF
X:$00 1000
On-Chip Data Flash
8KB
X:$00 0FFF
X:$00 0000
On-Chip Data RAM
8KB
3
3.
The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle long-word operations.
Table 4-5 Interrupt Vector Table Contents
1
(Continued)
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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