參數(shù)資料
型號： MC56F8345
廠商： Motorola, Inc.
英文描述： 56F8345 16-bit Hybrid Controller
中文描述： 56F8345 16位混合控制器
文件頁數(shù)： 109/148頁
文件大?。?/td> 1420K
代理商： MC56F8345
Clock Generation Overview
56F8345 Technical Data
Preliminary
109
6.6 Clock Generation Overview
The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the
peripheral and system (core and memory) clocks. The maximum master clock frequency is
120MHz. Peripheral and system clocks are generated at half the master clock frequency and
therefore at a maximum 60MHz. The SIM provides power modes (Stop, Wait) and clock enables
(SIM_PCE register, CLK_DIS, ONCE_EBL) to control which clocks are in operation. The OCCS,
power modes, and clock enables provide a flexible means to manage power consumption.
Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may
be shut down when not in use. When the PLL is in use, its prescaler and postscaler can be used to
limit PLL and master clock frequency. Power modes permit system and/or peripheral clocks to be
disabled when unused. Clock enables provide the means to disable individual clocks. Some
peripherals provide further controls to disable unused subfunctions. Refer to
Part 3 On-Chip
Clock Synthesis (OCCS)
and the
56F8300 Peripheral User Manual
for further details.
6.7 Power-Down Modes Overview
The 56F8345 operates in one of three power-down modes, as shown in
Table 6-3
.
All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the
same as the main processor frequency in this architecture. The maximum frequency of operation
is SYS_CLK = 60MHz.
Table 6-3 Clock Operation in Power-Down Modes
Mode
Core Clocks
Peripheral Clocks
Description
Run
Active
Active
Device is fully functional
Wait
Core and memory
clocks disabled
Active
Peripherals are active and can produce interrupts if
they have not been masked off.
Interrupts will cause the core to come out of its
suspended state and resume normal operation.
Typically used for power-conscious applications.
Stop
System clocks continue to be generated in
the SIM, but most are gated prior to
reaching memory, core and peripherals.
The only possible recoveries from Stop mode are:
1. CAN traffic (1st message will be lost)
2. Non-clocked interrupts
3. COP reset
4. External reset
5. Power-on reset
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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MC56F8345MFG60 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8345MFGE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz/60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8345VFG60 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8345VFGE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8346 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
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