參數(shù)資料
型號: MC56F8322VFAER2
廠商: Freescale Semiconductor
文件頁數(shù): 124/136頁
文件大?。?/td> 0K
描述: IC HYBRID CTRLR 16BIT 48-LQFP
標準包裝: 2,000
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,SCI,SPI
外圍設備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 40KB(20K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 帶卷 (TR)
配用: MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
56F8322 Techncial Data, Rev. 16
88
Freescale Semiconductor
Preliminary
As shown in Figure 6-10, the GPIO has the final control over which pin controls the I/O. SIM_GPS simply
decides which peripheral will be routed to the I/O.
Figure 6-10 Overall Control of Pads Using SIM_GPS Control
Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)
6.5.8.1
Reserved—Bits 15–8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2
GPIO C6 (C6)—Bit 7
This bit selects the alternate function for GPIOC6.
0 = TC0 (default)
1 = TXD0
6.5.8.3
GPIOC5 (C5)—Bit 6
This bit selects the alternate function for GPIOC5.
0 = TC1 (default)
1 = RXD0
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
C6
C5
B1
B0
A5
A4
A3
A2
Write
RESET
00
0
GPIOX_PER Register
GPIO Controlled
I/O Pad Control
SIM_GPS Register
Quad Timer Controlled
SCI Controlled
0
1
0
1
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
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