參數(shù)資料
型號(hào): MC56F8037EVM
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 3/180頁(yè)
文件大小: 0K
描述: BOARD EVAL FOR MC56F8037
標(biāo)準(zhǔn)包裝: 1
類型: MCU
適用于相關(guān)產(chǎn)品: MC56F8037
所含物品: 板,線纜,CD,調(diào)試程序
產(chǎn)品目錄頁(yè)面: 734 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: MC56F8037VLH-ND - IC DSP 16BIT DUAL 64-LQFP
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56F8037/56F8027 Data Sheet, Rev. 8
100
Freescale Semiconductor
6.3.6
SIM Power Control Register (SIM_PWR)
This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives
the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the
large regulator may be put in a reduced-power standby mode without interfering with device operation to
reduce device power consumption. Refer to the overview of power-down modes and the overview of clock
generation for more information on the use of large regulator standby.
Figure 6-7 SIM Power Control Register (SIM_PWR)
6.3.6.1
Reserved—Bits 15–2
This bit field is reserved. Each bit must be set to 0.
6.3.6.2
Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0
00 = Large regulator is in Normal mode
01 = Large regulator is in Standby (reduced-power) mode
10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset
11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset
6.3.7
Clock Output Select Register (SIM_CLKOUT)
The Clock Output Select register can be used to multiplex out selected clock sources generated inside the
clock generation and SIM modules onto the muxed clock output pins. All functionality is for test purposes
only. Glitches may be produced when the clock is enabled or switched. The delay from the clock source
to the output is unspecified. The observability of the CLKO clock output signal at an output pad is subject
to the frequency limitations of the associated IO cell.
GPIOA[3:0] can function as GPIO, PWM, or as clock output pins. If GPIOA[3:0] are programmed to
operate as peripheral outputs, then the choice is between PWM and clock outputs. The default state is for
the peripheral function of GPIOA[3:0] to be programmed as PWM (selected by bits [9:6] of the Clock
Output Select register).
GPIOB4 can function as GPIO, or as other peripheral outputs, including clock output (CLKO). If GPIOB4
is programmed to operate as a peripheral output and CLKO is selected in the SIM_GPSB0 register, bits
[4:0] decide if CLKO is enabled or disabled and which clock source is selected if CLKO is enabled. See
Figure 6-8 for details.
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
LRSTDBY
Write
RESET
0
000
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8037EVM 制造商:Freescale Semiconductor 功能描述:MC56F8037 EVALUATION BRD
MC56F8037MLH 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT DSPHC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8037VLH 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT DSPHC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F8037VLHR 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT DSPHC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MC56F80XXRM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Digital Signal Controller Product Brief