參數(shù)資料
型號: MC56F8033VLC
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
封裝: ROHS COMPLIANT, PLASTIC, LQFP-32
文件頁數(shù): 147/157頁
文件大?。?/td> 2117K
代理商: MC56F8033VLC
Award-Winning Development Environment
56F8033/56F8023 Data Sheet, Rev. 6
Freescale Semiconductor
9
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient, compact
DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F8033/56F8023 supports program execution from internal memories. Two data operands can be
accessed from the on-chip data RAM per instruction cycle. The 56F8033/56F8023 also offers up to 26
General-Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F8033 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified
Data/Program RAM. The 56F8023 Digital Signal Controller includes 32KB of Program Flash and 4KB of
Unified Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.
Program Flash page erase size is 512 Bytes (256 Words).
1.3 Award-Winning Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and
development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs
create a complete, scalable tools solution for easy, fast, and efficient development.
A full set of programmable peripherals — PWM, ADCs, QSCI, QSPI, I2C, PIT, Quad Timers, DACs, and
analog comparators — supports various applications. Each peripheral can be independently shut down to
save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).
1.4 Architecture Block Diagram
The 56F8033/56F8023’s architecture is shown in Figures 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7. Figure 1-1
illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and
the internal connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and
control blocks connected to the IPBus Bridge. Figures 1-3, 1-4, 1-5, 1-6, and 1-7 detail how the device’s
I/O pins are muxed. The figures do not show the on-board regulator and power and ground signals. Please
see Part 2, Signal/Connection Descriptions, for information about which signals are multiplexed with
those of other peripherals.
1.4.1
PWM, TMR and ADC Connections
Figure 1-6 shows the over-limit and under-limit connections from the ADC to the PWM and the
connections to the PWM from the TMR and GPIO. These signals can control the PWM outputs in a similar
manner as the PWM generator. See the 56F802X and 56F803X Peripheral Reference Manual for
additional information.
The PWM_reload_sync output can be connected to the Timer’s Channel 3 input and the Timer’s Channels
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