參數(shù)資料
型號： MC56F8033VLC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32
封裝： ROHS COMPLIANT, PLASTIC, LQFP-32
文件頁數(shù)： 141/157頁
文件大?。?/td> 2117K
代理商： MC56F8033VLC
56F8033/56F8023 Data Sheet, Rev. 6
84
Freescale Semiconductor
Figure 6-8 CLKO Select Register (SIM_CLKOUT)
6.3.7.1
Reserved—Bits 15–10
This bit field is reserved. Each bit must be set to 0.
6.3.7.2
PWM3—Bit 9
0 = Peripheral output function of GPIOA[3] is defined to be PWM3
1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock
6.3.7.3
PWM2—Bit 8
0 = Peripheral output function of GPIOA[2] is defined to be PWM2
1 = Peripheral output function of GPIOA[2] is defined to be the system clock
6.3.7.4
PWM1—Bit 7
0 = Peripheral output function of GPIOA[1] is defined to be PWM1
1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock
6.3.7.5
PWM0—Bit 6
0 = Peripheral output function of GPIOA[0] is defined to be PWM0
1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock
6.3.7.6
Clockout Disable (CLKDIS)—Bit 5
0 = CLKOUT output function is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT output function is disabled
6.3.7.7
Clockout Select (CLKOSEL)—Bits 4–0
CLKOSEL selects the clock to be muxed out on the CLKO pin as defined in the following. Internal delay
to CLKO output is unspecified. Signal at the output pad is undefined when CLKO signal frequency
exceeds the rated frequency of the I/O cell. CLKO may not operate as expected when CLKDIS and
CLKOSEL settings are changed.
00000 = Continuous system clock
00001 = Continuous peripheral clock
00010 = 3X system clock
00100.....11111 = Reserved for factory test
6.3.8
Peripheral Clock Rate Register (SIM_PCR)
By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PWM3PWM2PWM1PWM0
CLK
DIS
CLKOSEL
Write
RESET
0
1
0
0000
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