參數(shù)資料
型號: MC56F8011VFAE
廠商: Freescale Semiconductor
文件頁數(shù): 87/126頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 32-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 12KB(6K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 32-LQFP
包裝: 托盤
配用: CPA56F8013-ND - BOARD SOCKET FOR MC56F8013
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
Resets
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
63
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
5.5.16.4
Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
0 = Normal operation (default)
1 = All interrupts disabled
5.5.16.5
Reserved—Bits 4–2
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.5.16.6
Reserved—Bits 1–0
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6 Resets
5.6.1
General
5.6.2
Description of Reset Operation
5.6.2.1
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in Figure 5-19.
Figure 5-19 Reset Interface
Table 5-4 Reset Summary
Reset
Priority
Source
Characteristics
Core Reset
RST
Core reset from the SIM
RES
CLK
VAB
PAB
RESET_VECTOR_ADR
READ_ADR
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