參數資料
型號: MC56F8011VFAE
廠商: Freescale Semiconductor
文件頁數: 102/126頁
文件大小: 0K
描述: IC DIGITAL SIGNAL CTLR 32-LQFP
標準包裝: 250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數: 26
程序存儲器容量: 12KB(6K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數據轉換器: A/D 6x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 32-LQFP
包裝: 托盤
配用: CPA56F8013-ND - BOARD SOCKET FOR MC56F8013
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
Register Descriptions
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
77
6.3.9.4
Reserved—Bits 12–7
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.5
Timer Clock Enable (TMR)—Bit 6
0 = The clock is not provided to the Quad Timer module(the Quad Timer module is disabled)
1 = Clocks to the Quad Timer module are enabled
6.3.9.6
Reserved—Bit 5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.7
SCI Clock Enable (SCI)—Bit 4
0 = The clock is not provided to the SCI module (the SCI module is disabled)
1 = Clocks to the SCI module are enabled
6.3.9.8
Reserved—Bit 3
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.9
SPI Clock Enable (SPI)—Bit 2
0 = The clock is not provided to the SPI module (the SPI module is disabled)
1 = Clocks to the SPI module are enabled
6.3.9.10
Reserved—Bit 1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.11
PWM Clock Enable (PWM)—Bit 0
0 = The clock is not provided to the PWM module (the PWM module is disabled)
1 = Clocks to the PWM module are enabled
6.3.10
I/O Short Address Location Register (SIM_IOSAHI and
SIM_IOSALO)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in Figure 6-12.
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