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參數(shù)資料
| 型號(hào)： | MC54HC595 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs |
| 中文描述： | 8位Serial-Input/Serial或并行輸出移位與鎖存3注冊(cè)態(tài)輸出 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 297K |
| 代理商： | MC54HC595 |
MC54/74HC595A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
Symbol
VOH
Parameter
Test Conditions
V
25 C
85 C
2.0
Unit
V
Minimum High–Level Output
Vin = VIH or VIL
1.9
1.9
125 C
1.9
5.2 mA
5.48
5.34
5.2
Vin = VIH or VIL
IIoutI
6.0
2.0
6.0
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
4.0 mA
0.26
0.33
0.4
Vin = VIL or VIH
IIoutI
4.5
Current, QA – QH
Symbol
Parameter
V
25 C
85 C
6.0
35
28
125 C
4.0
24
fmax
Maximum Clock Frequency (50% Duty Cycle)
2.0
6.0
4.8
Unit
MHz
tPLH,
Maximum Propagation Delay, Shift Clock to SQH
2.0
140
175
210
ns
2.0
145
180
220
ns
tPHL
(Figures 3 and 7)
4.5
28
42
tPHZ
(Figures 4 and 8)
4.5
30
35
45
(Figures 4 and 8)
4.5
27
38
41
6.0
10
34
15
tTLH,
Maximum Output Transition Time, SQH
2.0
6.0
75
13
13
110
19
ns
Cin
Cout
Maximum Input Capacitance
Maximum Three–State Output Capacitance (Output in
Speed CMOS Data Book (DL129/D).
—
—
10
15
95
16
10
15
pF
pF
10
15
CPD
Power Dissipation Capacitance (Per Package)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
300
pF
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| MC54HC595AJ | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs |
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| MC54HC597J | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:8-Bit Serial or Parallel-Input/Serial-Output Shift Register with Input Latch |
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