參數(shù)資料
型號(hào)： MC44724VFU
廠商： Motorola, Inc.
英文描述： Digital Video Encoder
中文描述： 數(shù)字視頻編碼器
文件頁數(shù)： 37/39頁
文件大小： 518K
代理商： MC44724VFU
MC44724/5 Rev 0.21 03/25/97
No.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
37
70h:[7]
[6]
[5]
[4]
[3]
[2]
[1:0]
71h:[7]
burst control (default 0:on)
self counter reset switch (default 0:off)
color bar select (defalut 0:Luma 100% Chroma 100%)
vertical blanking switch(default 0:off)
EXT pin output mode select (Csync:1, Flame sync:0)
F/Vsync select(default 0:Vsync)
Master/Slave mode select(default 01:656_slave)
interlaced / non-interlaced
(default 0:interlaced)
VBI input control on EXT pin (default 0:off)
horizontal sync polarity (default 0)
vertical sync polarity (default 0)
flame sync polarity (default 0)
hsync delay control (default 100:0 clock delay)
(In slave mode can use with 7A[7:0])
sub-currier phase syncronaiation(default 0)
Test mode (default 0:off)
EXT I/O switch(defalt 1:cysnc output)
color bar generate(default 0:off)
setup level control(default 1:7.5IRE)
625lines50Hz/525Lines60Hz
(default set PAL/NTSC pin)
PAL/NTSC (default set PAL/NTSC pin)
00:NTSC/M
01:PAL/BGHL
(10:PAL/M) (11:PAL/N)
Y_register(default 80h)
U_register(default 79d:ntsc/157d:PAL)
V_register(default 128d:ntsc/107d:PAL)
Cr on/off (default 0:on)
Cb on/off (default 0:on)
Luma on/off(default 0:on)
(default 0: on)
CVBS dac/Cdac/Ydac on/off(default 0: on)
D/A converter output signal control
(default 00 : CBVS/Y/C output)
[6]
[5]
[4]
[3]
[2:0]
72h:[7]
[6]
[5]
[4]
[3]
[2]
[1:0]
73h[7:0]
74h[7:0]
75h[7:0]
76h[7]
[6]
[5]
[4:2]
[1:0]
77h[7:5]
[4:2]
[1:0]
B/R/G signal control (default 0: On)
D/A converter(2) output On/Off control(default 0: On)
D/A converter(2) output signal control(default 0X: On)
78h[7:0]
79h[1:0]
79h[7:2]
sub-currier phase control(default 00h)
sub-currier phase control(default 00)
n.a.
7A[7:0]
hsync-delay control
(In slave mode, is valid with 71h[2:0] register)
n.a
Cr/Cb clock timing delay in 16-bit digital input mode
(default 00: clock delay 0)
Y clock timing delay in 16-bit digital input mode
(default 0: clock delay 0)
16-bit multiplexed CbYCrYdigital video input mode
(default 0: 8-bit YCrCb digital video input mode)
Ysync signal On/Off(YCrCb mode only)(default 0: On)
R/Bsync signal On/Of(default 0: Off)
Gsync signal On/Of(default 0: Off)
R/B CGMS data insertion On/Of(default 0: On)
G CGMS data insertion On/Of(default 0: On)
RGB/CbCr burst On/Off(default 0: On)
Chroma burst On/Off(default 0: On)
7B[7:6]
[5:2]
[1]
[0]
7C[7]
[6]
[5]
[4]
[3]
[2:1]
[0]
7D[7:0]
delay on Vsync with reference to DVIN data in slave
mode
n.a
delay on Vsync with reference to DVIN data in slave
mode
7E[7:2]
[1:0]
80~82h
80~81h
83h[7:0]
84h[7:0]
85h[7:0]
86h[7:0]
87h[7:6]
[5]
[4]
[3]
[2]
[1]
CGMS characters for field1(line20)/field2(line283)
WSS characters for field1(line23)
CC character1(line21) (default 'h80)
CC character2(line21) (default 'h80)
CC character1(line284) (default 'h80)
CC character2(line284) (default 'h80)
Closed Caption Status Flag for field2
Automatic set to null code(Closed Caption data)
n.a.
WSS information data insetion on/off (default 0: off)
CGMS on/off (default 0: off)
CC closed caption/extended data for field2 encoding
(default 0: off)
CC closed caption/extended data for field1 encoding
(default 0: off)
[0]
2C-BUS Slave Receiver Sub-address map
** WRITE MODE **
S | Slave_address(W) | A | Sub_address | A | Data0 | A | ... | DataN | A | P
S
Start condition
Slave_address
42(hex) or 1C(hex)
A
Acknowledge generated by me
Sub_address
Sub_address register
Data0
First data
DataN
Continued data(address is auto incremented)
P
Stop condition
<<<<<<<< SPI-Bus Format >>>>>>
** WRITE MODE **
S | Write Command | Sub_address | Data0 | ... | DataN | P
S
Chip select on (High to Low)
Write Command
42(hex) or 1C(hex)
Sub_address
Sub_address byte
Data0
First data
DataN
Continued data byte(address is auto incremented)
P
Chip select off (Low to High)
<<<<<<<< M-BUS Format >>>>>>
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