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參數(shù)資料
| 型號： | MC14553BDW |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Single Channel (1.5V) SVS with /MR in 5/SOT23 5-SOT-23 -40 to 85 |
| 中文描述： | 4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 12-BIT UP DECADE COUNTER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 178K |
| 代理商： | MC14553BDW |
MC14553B
http://onsemi.com
4
(6.)
(7.)
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
2a
t
TLH
,
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Clock to BCD Out
2a
t
PLH
,
t
PHL
5.0
10
15
—
—
—
900
500
200
1800
1000
400
ns
Clock to Overflow
2a
t
PHL
5.0
10
15
—
—
—
600
400
200
1200
800
400
ns
Reset to BCD Out
2b
t
PHL
5.0
10
15
—
—
—
900
500
300
1800
1000
600
ns
Clock to Latch Enable Setup Time
Master Reset to Latch Enable Setup Time
2b
t
su
5.0
10
15
600
400
200
300
200
100
—
—
—
ns
Removal Time
Latch Enable to Clock
2b
t
rem
5.0
10
15
– 80
– 10
0
– 200
– 70
– 50
—
—
—
ns
Clock Pulse Width
2a
t
WH(cl)
5.0
10
15
550
200
150
275
100
75
—
—
—
ns
Reset Pulse Width
2b
t
WH(R)
5.0
10
15
1200
600
450
600
300
225
—
—
—
ns
Reset Removal Time
—
t
rem
5.0
10
15
– 80
0
20
– 180
– 50
– 30
—
—
—
ns
Input Clock Frequency
2a
f
cl
5.0
10
15
—
—
—
1.5
5.0
7.0
0.9
2.5
3.5
MHz
Input Clock Rise Time
2b
t
TLH
5.0
10
15
No
Limit
ns
Disable, MR, Latch Enable
Rise and Fall Times
—
t
TLH
,
t
THL
5.0
10
15
—
—
—
—
—
—
15
5.0
4.0
μ
s
Scan Oscillator Frequency
(C1 measured in
μ
F)
1
f
osc
5.0
10
15
—
—
—
1.5/C1
4.2/C1
7.0/C1
—
—
—
Hz
6. The formulas given are for the typical characteristics only at 25 C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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| MC14555BCP | 功能描述:編碼器、解碼器、復(fù)用器和解復(fù)用器 3-18V Dual Binary to RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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