參數(shù)資料
型號(hào): MC14553BDW
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Single Channel (1.5V) SVS with /MR in 5/SOT23 5-SOT-23 -40 to 85
中文描述: 4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 12-BIT UP DECADE COUNTER, PDSO16
封裝: SOIC-16
文件頁數(shù): 1/12頁
文件大?。?/td> 178K
代理商: MC14553BDW
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14553B/D
The MC14553B 3–digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 1.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5
V
I
in
Input Current
(DC or Transient) per Pin
±
10
mA
I
out
Output Current
(DC or Transient) per Pin
+20
mA
P
D
Power Dissipation,
per Package (Note 2.)
500
mW
T
A
Ambient Temperature Range
–55 to +125
°
C
T
stg
Storage Temperature Range
–65 to +150
°
C
T
L
Lead Temperature
(8–Second Soldering)
260
°
C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
WL or L
YY or Y
WW or W = Work Week
= Assembly Location
= Wafer Lot
= Year
Device
Package
Shipping
ORDERING INFORMATION
MC14553BCP
PDIP–16
25/Rail
MC14553BDW
SOIC–16
47/Rail
MARKING
DIAGRAMS
16
1
PDIP–16
P SUFFIX
CASE 648
MC14553BCP
AWLYYWW
SOIC–16
DW SUFFIX
CASE 751G
1
16
14553B
AWLYYWW
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